AD7492BRU-5(Rev0) 查看數據表（PDF） - Analog Devices
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AD7492BRU-5 Datasheet PDF : 16 Pages
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AD7492
Figure 15 to Figure 17 show a typical graphical representation
of Power versus Throughput for the AD7492 when in (a) Mode
1 @ 5 V and 3 V, (b) Mode 2 in full sleep mode @ 5 V and 3 V
and (c) Mode 2 in partial sleep mode @ 5 V and 3 V.
12
10
5V
8
6
4
3V
2
0
0 100 200 300 400 500 600 700 800 900 1000
THROUGHPUT – kHz
Figure 15. Power vs. Throughput (Mode 1 @ 5 V and 3 V)
3.5
3.0
GROUNDING AND LAYOUT
The analog and digital power supplies are independent and
separately pinned out to minimize coupling between analog and
digital sections within the device. To complement the excellent
noise performance of the AD7492 it is imperative that care be
given to the PCB layout. Figure 18 shows a recommended
connection diagram for the AD7492.
All of the AD7492 ground pins should be soldered directly to a
ground plane to minimize series inductance. The AVDD, DVDD,
and VDRIVE pins should be decoupled to both the analog and
digital ground planes. The REF OUT pin should be decoupled
to the analog ground plane with a minimum capacitor value of
100 nF. This capacitor helps to stabilize the internal reference
circuit. The large value capacitors will decouple low frequency
noise to analog ground, the small value capacitors will decouple
high frequency noise to digital ground. All digital circuitry power
pins should be decoupled to the digital ground plane. The use
of ground planes can physically separate sensitive analog com-
ponents from the noisy digital system. The two ground planes
should be joined in only one place and should not overlap so as
to minimize capacitive coupling between them. If the AD7492
is in a system where multiple devices require AGND to DGND
connections, the connection should still be made at one point
only, a star ground point, that should be established as close as
possible to the AD7492.
2.5
2.0
5V
1.5
3V
1.0
0.5
0
0 10 20 30 40 50 60 70 80 90 100
THROUGHPUT – kHz
Figure 16. Power vs. Throughput (Mode 2 in Full Sleep
Mode @ 5 V and 3 V)
2.5
2.0
5V
1.5
3V
1.0
0.5
0
0 10 20 30 40 50 60 70 80 90 100
THROUGHPUT – kHz
Figure 17. Power vs. Throughput (Mode 2 in Partial
Sleep Mode @ 5 V and 3 V)
+
10F
0.1F
AVDD
DVDD
1nF
AGND
AD7492
DGND
+
VDRIVE
1nF 10F
+
47F
ANALOG
SUPPLY
5V
2.5V
+
100nF
REF OUT
Figure 18. Typical Decoupling Circuit
Noise can be minimized by applying some simple rules to the
PCB layout: analog signals should be kept away from digital
signals; fast switching signals like clocks should be shielded with
digital ground to avoid radiating noise to other sections of the
board and clock signals should never be run near the analog
inputs; avoid running digital lines under the device as these will
couple noise onto the die; the power supply lines to the AD7492
should use as large a trace as possible to provide a low imped-
ance path and reduce the effects of glitches on the power supply
line; avoid crossover of digital and analog signals and place
traces that are on opposite sides of the board at right angles
to each other.
Noise to the analog power line can be further reduced by use of
multiple decoupling capacitors as shown in Figure 18. Decou-
pling capacitors should be placed directly at the power inlet to
the PCB and also as close as possible to the power pins of the
AD7492. The same decoupling method should be used on other
ICs on the PCB, with the capacitor leads as short as possible to
minimize lead inductance.
REV. 0
–13–
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