AD7492BRU-5(Rev0) 查看數據表（PDF） - Analog Devices
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AD7492BRU-5 Datasheet PDF : 16 Pages
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AD7492
POWER SUPPLIES
Separate power supplies for AVDD and DVDD are desirable, but
if necessary, DVDD may share its power connection to AVDD.
The digital supply (DVDD) must not exceed the analog supply
(AVDD) by more than 0.3 V in normal operation.
MICROPROCESSOR INTERFACING
AD7492 to ADSP-2185 Interface
Figure 19 shows a typical interface between the AD7492 and the
ADSP-2185. The ADSP-2185 processor can be used in one of two
memory modes, Full Memory Mode and Host Mode. The Mode
C pin determines in which mode the processor works. The inter-
face in Figure 19 is set up to have the processor working in Full
Memory Mode, which allows full external addressing capabilities.
When the AD7492 has finished converting, the BUSY line
requests an interrupt through the IRQ2 pin. The IRQ2 interrupt
has to be set up in the interrupt control register as edge-sensitive.
The DMS (Data Memory Select) pin latches in the address of the
A/D into the address decoder. The read operation is thus started.
OPTIONAL
A0–A15
ADDRESS BUS
ADSP-2185*
DMS
ADDRESS
DECODER
IRQ2
RD
100k⍀
MODE C
D0–D23
DATA BUS
CONVST
AD7492
CS
BUSY
RD
DB0–DB9
(DB11)
*ADDITIONAL PINS OMITTED FOR CLARITY
AD7492 to TMS320C25 Interface
Figure 21 shows an interface between the AD7492 and the
TMS320C25. The CONVST signal can be applied from the
TMS320C25 or from an external source. The BUSY line inter-
rupts the digital signal processor when conversion is completed.
The TMS320C25 does not have a separate RD output to drive
the AD7492 RD input directly. This has to be generated from
the processor STRB and R/W outputs with the addition of some
glue logic. The RD signal is OR-gated with the MSC signal to
provide the WAIT state required in the read cycle for correct
interface timing. The following instruction is used to read the
conversion from the AD7492:
IN D,ADC
where D is Data Memory address and the ADC is the AD7492
address. The read operation must not be attempted during
conversion.
OPTIONAL
A0–A15
TMS320C25*
IS
ADDRESS BUS
ADDRESS
DECODER
STRB
R/W
READY
MSC
DMD0–DMD15
DATA BUS
CONVST
AD7492
CS
BUSY
RD
DB0–DB9
(DB11)
Figure 19. Interfacing to the ADSP-2185
AD7492 to ADSP-21065L Interface
Figure 20 shows a typical interface between the AD7492 and the
ADSP-21065L SHARC® processor. This interface is an example
of one of three DMA handshake modes. The MSX control line
is actually three memory select lines. Internal ADDR25–24 are
decoded into MS3-0, these lines are then asserted as chip selects.
The DMAR1 (DMA Request 1) is used in this setup as the
interrupt to signal end of conversion. The rest of the interface is
standard handshaking operation.
OPTIONAL
ADDR0–ADDR23
ADDRESS BUS
CONVST
MSX
ADSP-21065L*
DMAR1
RD
ADDRESS
LATCH
ADDRESS
BUS
ADDRESS
DECODER
D0–D31
DATA BUS
AD7492
CS
BUSY
RD
DB0–DB9
(DB11)
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. Interfacing to ADSP-21065L
SHARC is a registered trademark of Analog Devices, Inc.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. Interfacing to the TMS320C25
AD7492 to PIC17C4x Interface
Figure 22 shows a typical parallel interface between the AD7492
and PIC17C42/43/44. The microcontroller sees the A/D as
another memory device with its own specific memory address on
the memory map. The CONVST signal can either be controlled
by the microcontroller or an external source. The BUSY signal
provides an interrupt request to the microcontroller when a con-
version ends. The INT pin on the PIC17C42/43/44 must be
configured to be active on the negative edge. PORTC and PORTD
of the microcontroller are bidirectional and used to address the
AD7492 and also to read in the 12-bit data. The OE pin on the
PIC can be used to enable the output buffers on the AD7492 and
preform a read operation.
OPTIONAL
PIC17C4x*
AD0–AD15
ALE
OE
INT
ADDRESS
LATCH
ADDRESS
DECODER
CONVST
DB0–DB9
(DB11)
AD74792
CS
RD
BUSY
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. Interfacing to the PIC17C4x
–14–
REV. 0
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