AD7492BR-5(Rev0) 查看數據表（PDF） - Analog Devices
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AD7492BR-5 Datasheet PDF : 16 Pages
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AD7492
Pin
1–3,
13–18,
22–24
4
5
6
7
8
Mnemonic
DB9–DB11,
DB0–DB5,
DB6–DB8
AVDD
REF OUT
VIN
AGND
CS
9
RD
10
CONVST
11
PS/FS
12
BUSY
19
DGND
20
DVDD
21
VDRIVE
PIN FUNCTION DESCRIPTION
Function
Data Bit 0 to DB11. Parallel digital outputs that provide the conversion result for the part. These
are three-state outputs that are controlled by CS and RD. The output high voltage level for these
outputs is determined by the VDRIVE input.
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on
the AD7492. The AVDD and DVDD voltages should ideally be at the same potential and must not
be more than 0.3 V apart, even on a transient basis. This supply should be decoupled to AGND.
Reference Out. The output voltage from this pin is 2.5 V ± 1%.
Analog Input. Single-ended analog input channel. The input range is 0 V to REFIN. The analog
input presents a high dc input impedance.
Analog Ground. Ground reference point for all analog circuitry on the AD7492. All analog input
signals should be referred to this AGND voltage. The AGND and DGND voltages should
ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
Chip Select. Active low logic input used in conjunction with RD to access the conversion result.
The conversion result is placed on the data bus following the falling edge of both CS and RD.
CS and RD are both connected to the same AND gate on the input so the signals are inter-
changeable. CS can be hardwired permanently low.
Read Input. Logic input used in conjunction with CS to access the conversion result. The con-
version result is placed on the data bus following the falling edge of both CS and RD. CS and
RD are both connected to the same AND gate on the input so the signals are interchangeable.
CS and RD can be hardwired permanently low, in which case the data bus is always active and
the result of the new conversion is clocked out slightly before to the BUSY line going low.
Conversion Start Input. Logic input used to initiate conversion. The input track/hold amplifier
goes from track mode to hold mode on the falling edge of CONVST and the conversion process
is initiated at this point. The conversion input can be as narrow as 10 ns. If the CONVST input
is kept low for the duration of conversion and is still low at the end of conversion, the part will
automatically enter a sleep mode. The type of sleep mode is determined by the PS/FS pin. If the
part enters a sleep mode, the next rising edge of CONVST wakes up the part. Wake-up time
depends on the type of sleep mode.
Partial Sleep/Full Sleep Mode. This pin determines the type of sleep mode the part will enter if
the CONVST pin is kept low for the duration of the conversion and is still low at the end of
conversion. In partial sleep mode the internal reference circuit and oscillator circuit is not pow-
ered down and draws 250 µA maximum. In full sleep mode all of the analog circuitry is
powered down and the current drawn is negligible. This pin is hardwired either high (DVDD) or
low (GND).
BUSY Output. Logic output indicating the status of the conversion process. The BUSY signal
goes high after the falling edge of CONVST and stays high for the duration of conversion. Once
conversion is complete and the conversion result is in the output register, the BUSY line returns
low. The track/hold returns to track mode just prior to the falling edge of BUSY and the acquisi-
tion time for the part begins when BUSY goes low. If the CONVST input is still low when BUSY
goes low, the part automatically enters its sleep mode on the falling edge of BUSY.
Digital Ground. This is the ground reference point for all digital circuitry on the AD7492. The
DGND and AGND voltages should ideally be at the same potential and must not be more than
0.3 V apart, even on a transient basis.
Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the
AD7492 apart from the output drivers and input circuitry. The DVDD and AVDD voltages
should ideally be at the same potential and must not be more than 0.3 V apart even on a tran-
sient basis. This supply should be decoupled to DGND.
Supply Voltage for the Output Drivers and Digital Input circuitry, 2.7 V to 5.25 V. This voltage
determines the output high voltage for the data output pins and the trigger levels for the digital
inputs. It allows the AVDD and DVDD to operate at 5 V (and maximize the dynamic performance
of the ADC) while the digital input and output pins can interface to 3 V logic.
–6–
REV. 0
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