AD7538(RevA) 查看數據表（PDF） - Analog Devices
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AD7538 Datasheet PDF : 8 Pages
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AD7538–SPECIFICATIONS1 (VDD = +11.4 V to +15.75 V2, VREF = +10 V; VPIN3 = VPIN4 = 0 V,
VSS = –300 mV. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
J, K
Versions
A, B
Versions
S Version T Version Units
Test Conditions/Comments
ACCURACY
Resolution
14
Relative Accuracy
±2
Differential Nonlinearity
±1
Full-Scale Error
+25°C
±4
TMIN to TMAX
±8
Gain Temperature Coefficient3;
∆Gain/∆Temperature
±2
Output Leakage Current IOUT (Pin 3)
+25°C
±5
TMIN to TMAX
TMIN to TMAX
± 10
± 25
14
14
14
Bits
±1
±2
±1
LSB max
All Grades Guaranteed Monotonic
±1
±1
±1
LSB max
Over Temperature.
Measured Using Internal RFB DAC
±4
±4
±4
LSB max
Registers Loaded with All 1s.
±5
± 10
±6
LSB max
±2
±2
±2
ppm/°C typ
±5
±5
±5
nA max
± 10
± 20
± 20
nA max
± 25
± 150
± 150
nA max
All Digital Inputs 0 V
VSS = –300 mV
VSS = 0 V
REFERENCE INPUT
Input Resistance, Pin 1
3.5
3.5
3.5
3.5
kΩ min
10
10
10
10
kΩ max
Typical Input Resistance = 6 kΩ
DIGITAL INPUTS
VIH (Input High Voltage)
VIL (Input Low Voltage)
IIN (Input Current)
+25°C
TMIN to TMAX
CIN (Input Capacitance)3
2.4
2.4
2.4
2.4
V min
0.8
0.8
0.8
0.8
V max
±1
±1
±1
±1
µA max
± 10
± 10
± 10
± 10
µA max
7
7
7
7
pF max
VIN = 0 V or VDD
POWER SUPPLY
VDD Range
VSS Range
IDD
11.4/15.75
–200/–500
4
500
11.4/15.75
–200/–500
4
500
11.4/15.75
–200/–500
4
500
11.4/15.75
–200/–500
4
500
V min/V max
mV min/mV max
mA max
µA max
Specification Guaranteed Over
This Range
All Digital Inputs VIL or VIH
All Digital Inputs 0 V or VDD
These characteristics are included for Design Guidance only and are not sub-
AC PERFORMANCE CHARACTERISTICS ject to test. (VDD = +11.4 V to +15.75 V, VREF = +10 V, VPIN3 = VPIN4 = O V, VSS =
O V or –300 mV, Output Amplifier is AD711 except where noted.)
Parameter
TA = +25؇C TA = TMIN, TMAX
Units
Test Conditions/Comments
Output Current Settling Time
1.5
Digital to Analog Glitch Impulse 20
Multiplying Feedthrough Error
Power Supply Rejection
∆Gain/∆VDD
Output Capacitance
COUT (Pin 3)
COUT (Pin 3)
Output Noise Voltage Density
(10 Hz–100 kHz)
3
± 0.01
260
130
15
5
± 0.02
260
130
µs max
nV-sec typ
mV p-p typ
To 0.003% of Full-Scale Range.
IOUT Load= 100 Ω, CEXT = 13 pF.
DAC Register Alternately Loaded
with All 1s and All 0s. Typical Value
of Settling Time Is 0.8 µs.
Measured with VREF = 0 V. IOUT Load
= 100 Ω, CEXT = 13 pF. DAC Register
Alternately Loaded with All 1s and All 0s.
VREF = ± 10 V, 10 kHz Sine Wave DAC
Register Loaded with All 0s.
% per % max ∆VDD = ± 5%
pF max
pF max
DAC Register Loaded with All 1s
DAC Register Loaded with All 0s
nV√Hz typ
Measured Between RFB and IOUT
NOTES
Temperature range as follows: J, K Versions: 0°C to +70°C
A, B Versions: –25°C to +85°C
S, T Versions: –55°C to +125°C
2Specifications are guaranteed for a VDD of +11.4 V to +15.75 V. At VDD = 5 V, the device is fully functional with degraded specifications.
3Sample tested to ensure compliance.
Specifications subject to change without notice.
–2–
REV. A
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