AD7570 查看數據表（PDF） - Analog Devices
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AD7570 Datasheet PDF : 12 Pages
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(8
Table 2. Unipolar Operation
Table 3. Bipolar Operation
Analog Input
(AIN)
Notes 1, 2, 3
Digital Output Code
MSB
LSB
Analog Input
(AIN)
Notes 1, 2, 3
Digital Output Code
MSB
LSB
FS - lLSB
1111111111
+(FS - 1LSB)
1111111111
FS - 2LSB
1111111110
+(FS - 2LSB)
1111111110
3/4 FS
1100000000
+(1/2 FS)
1100000000
1/2 FS + lLSB
1000000001
+(1LSB)
1000000001
1/2 FS
1000000000
0
1000000000
1/2 FS - lLSB
01111 11 111
-(1LSB)
0111111111
1/4 FS
0100000000
-(1/2 FS)
0100000000
lLSB
0
0000000001
0000000000
NOTES:
(8 1. Analog inputs shown are nominal center values
of code.
O 2. "FS" is full scale, i.e., (-VREF)'
3. For 8-bit operation, lLSB equals (-VREF)
B(Z-8); for to-bit operation, lLSB equals
(-VREF) (2-10).
(8 SOL ADJUSTMENT PROCEDURES BIPOLAR OPERATION
ETE Gain Adjustment
-(FS - lLSB)
-FS
0000000001
0000000000
NOTES:
1. Analog inputs shown are nominal center values
of code.
2. "FS" is full scale; i.e., (VREF)'
3. For 8-bit operation, lLSB equals (-VREF)
(Z-7); for to-bit operation, lLSB equals
(-VREF) (2-9).
6. If an external clock is used, the negative transition of STRT
1. Apply continuous start commands to the STRT input of
should not coincide with the trailing edge of the clock
the AD7570.
input.
2. Apply 1-1/2LSB less than positive full scale (FS = VREF)
OPERA TING PRECAUTIONS
to the bipolar analog input of Figure 11.
1. Do not allow Vcc to exceed VDD' In cases where Vcc
3. Trim the gain potentiometer R4 for a flickering LSB, and
(8
all other data bits equal to Logic "1". Observe the SRO
terminal, as described in zero offset procedure above.
could exceed VDD' the diode protection scheme in Figure
12 is recommended.
2. Do not apply voltages greater than Vcc or lower than
ground to any digital output from sources which can sup-
APPLICATION HINTS
ply >20mA.
3. Do not apply voltages (from a source which can supply
more than SmA) lower than ground to the OUTI or OUT2
1. Unused CMOS digital inputs should be tied to their appro-
terminal (see Figure 12).
priate logic level and not left floating. Open digital inputs
may cause undesired digital activity in the presence of noise.
Vcc
Voo
2. Analog and digital grounds should have separate retUrns.
3. Load the OUTI terminal with a 1k resistor to reduce the
time constant when operating at clock frequencies
>50kHz.
4. For 10-bit operation, the comparator offset should be
adjusted to less than ImV. Each millivolt of comparator
(8
offset will cause approximately 0.015% of differential
nonlinearity when a 10V reference is used.
1N459,
1N914
HP5082-2811
22
AD7570
4 .OUT1
5. The comparator input and output should be isolated to
prevent oscillations due to stray capacitance. (See layout
on the next page).
Figure 12. Diode Protection Scheme
-9-
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