AD7625(RevPrB) 查看數據表（PDF） - Analog Devices
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AD7625 Datasheet PDF : 11 Pages
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AD7625
Preliminary Technical Data
Self Clocked Mode
The AD7626 digital operation in “self-clocked interface mode”
is shown in Figure 4. This interface mode reduces the number
of wires between ADCs and the digital host to 2 LVDS pairs per
AD7626, CLK± and D± or a single pair if sharing a common
CLK using multiple AD7626’s. This considerably eases the
design of a system using multiple AD7626’s since the interface
can tolerate several CLK cycles of propagation delay mismatch
between the different AD7626 devices and the digital host.
The “self-clocked interface mode” consists of preceding each
ADC word results by a header of 2 bits on the data, D This
header is used to synchronize D of each conversion in the
digital host. Synchronization is accomplished by one simple
state machine per AD7626 device. The state machine is running,
for instance, at the same speed as CLK with 3 phases. The state
machine measures when the first “one” of the header occurs.
This provides the value of the actual propagation delay delta
between the state machine clock and D including any board
propagation time allowing to use the best clock signal to latch
the following bits of the conversion result.
Conversions are initiated by a CNV pulse. The CNV must be
returned low ≤ tCNVH(max) for valid operation. Once a
conversion has begun, it continues until completion. Additional
CNV pulses are ignored during the conversion phase. After the
time tMSB elapses, the host should begin to burst the CLK. Note
that tMSB is the maximum time for the first bit of the header and
should be used as the gating device for CLK. CLK is also used
internally on the host to begin the internal synchronization
state machine. The next header bit and conversion results are
output on subsequent falling edges of CLK. The only
requirement is that the 18 CLK pulses finish before the time
tCLKL elapses of the next conversion phase or the data will be
lost.
CNV-
CNV+
SAMPLE N
TCNVH
TCYC
SAMPLE N+1
TACQ
ACQUISITION
ACQUISITION
ACQUISITION
TCLK
TCLKL
CLK-
17 18
1
2
3
4
17 18
1
2
3
CLK+
TCLKD
D+
D-
TMSB
D1
D0
N-1
N-1
*1
0
1
0 D15 D14
N
N
Figure 4. Self-Clocked Interface Mode Timing Diagram1
D1
D0
N
N
0
1
0 D15
N+1
1 This timing is for silicon rev 1 or above. For silicon rev 0, there is an extra bit (a zero) in front on the bit with value 1. Therefore, silicon rev 0 needs 19 clock pulses.
Rev. PrB | Page 10 of 11
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