AD76881 查看數據表（PDF） - Analog Devices
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AD76881 Datasheet PDF : 28 Pages
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CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7986 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 25, and the corresponding timing is given in
Figure 26.
With SDI tied to VIO, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. Once
a conversion is initiated, it continues until completion irrespective
of the state of CNV. This can be useful, for instance, to bring
CNV low to select other SPI devices, such as analog multiplexers;
however, CNV must be returned high before the minimum
AD7986
conversion time elapses and then held high for the maximum
possible conversion time to avoid the generation of the busy
signal indicator. When the conversion is complete, the AD7986
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate, provided that it has an acceptable hold
time. After the 18th SCK falling edge or when CNV goes high
(whichever occurs first), SDO returns to high impedance.
CNV
VIO
SDI AD7986 SDO
CONVERT
DIGITAL HOST
DATA IN
SCK
CLK
Figure 25. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
SDI = 1
CNV
ACQUISITION
(n - 1)
SCK
SDO
tDATA
> tCONV
tCONV
tCYC
tCONV
tDATA
tCNVH
tACQ
CONVERSION (n – 1)
(I/O QUIET
TIME)
ACQUISITION (n)
(QUIET
TIME)
CONVERSION (n)
16 17 18
tEN
210
tDIS END DATA (n – 2)
tDIS
12
tHSDO
tEN
tDSDO
17 16 15
BEGIN DATA (n – 1)
tQUIET
16 17 18
tSCK
21 0
tDIS END DATA (n – 1)
Figure 26. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
(I/O QUIET ACQUISITION
TIME)
(n + 1)
tDIS
Rev. B | Page 19 of 28
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