AD7765(Rev0) 查看數據表（PDF） - Analog Devices

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AD7765
(Rev.:Rev0)

24-Bit, 156 kSPS, 112 dB Σ-Δ ADC with On-Chip Buffers and Serial Interface

Analog Devices 

AD7765

TIMING DIAGRAMS

SCO (O)

FSO (O)

SDO (O)

32 × tSCO

t1

t3

t4

t5

D23 D22

t2

t6

D21 D20

t7

D19

t9

D1

D0

ST4 ST3 ST2 ST1 ST0

0

Figure 2. Serial Read Timing Diagram

t8

0

0

SCO (O)

FSI (I)

SDI (I)

t1

t2

t12

t10

t11

t13

t14

t15

RA15 RA14 RA13 RA12 RA11 RA10 RA9

RA8

RA1 RA0 D15 D14

Figure 3. AD7765 Register Write

D1

D0

SCO (O)

FSO (O)

SDO (O)

FSI (I)

SDI (I)

≥8 × tSCO

STATUS REGISTER

CONTENTS [31:16]

DON’T CARE

BITS [15:0]

NEXT DATA READ FOLLOWING THE WRITE TO CONTROL REGISTER

CONTROL REGISTER

ADDR (0x0001)

CONTROL REGISTER

INSTRUCTION

Figure 4. AD7765 Status Register Read Cycle

Rev. 0 | Page 7 of 32

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