AD7801 查看數據表（PDF） - Analog Devices
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AD7801 Datasheet PDF : 16 Pages
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AD7801–SPECIFICATIONS (VDD = +2.7 V to +5.5 V, Internal Reference; CL = 100 pF, RL = 10 k⍀ to VDD and GND.
All specifications TMIN to TMAX unless otherwise noted.)
Parameter
B Versions1
Units
Conditions/Comments
STATIC PERFORMANCE
Resolution
Relative Accuracy2
Differential Nonlinearity
Zero-Code Error @ +25°C
Full-Scale Error
Zero-Code Error Drift
Gain Error3
8
±1
±1
3
–0.75
100
±1
Bits
LSB max
LSB max
LSB typ
LSB typ
µV/°C typ
% FSR typ
DAC REFERENCE INPUT
REFIN Input Range
REFIN Input Impedance
OUTPUT CHARACTERISTICS
Output Voltage Range
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DC Output Impedance
Short Circuit Current
Power Supply Rejection Ratio4
1 to VDD/2
10
0 to VDD
2
7.5
1
0.2
40
14
0.0003
V min/V max
MΩ typ
V min/V max
µs max
V/µs typ
nV-s typ
nV-s typ
Ω typ
mA typ
%/% max
LOGIC INPUTS
Input Current
± 10
VINL, Input Low Voltage
0.8
VINL, Input Low Voltage
0.6
VINH, Input High Voltage
2.4
VINH, Input High Voltage
2.1
Pin Capacitance
7
µA max
V max
V max
V min
V min
pF max
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 3.3 V
@ 25°C
TMIN to TMAX
VDD = 5.5 V
@ 25°C
TMIN to TMAX
IDD (Power-Down)
@ 25°C
TMIN to TMAX
2.7/5.5
1.55
1.75
2.35
2.5
1
2
V min/V max
mA max
mA max
mA max
mA max
µA max
µA max
NOTES
1Temperature ranges are as follows: B Version: –40°C to +105°C
2Relative Accuracy is calculated using a reduced code range of 15 to 245.
3Gain Error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB.
4Guaranteed by characterization at product release, not production tested.
Specifications subject to change without notice.
Guaranteed Monotonic
All Zeros Loaded to DAC Register
All Ones Loaded to DAC Register
Typically 1.2 µs
1 LSB Change Around Major Carry
∆VDD = ± 10%
VDD = +5 V
VDD = +3 V
VDD = +5 V
VDD = +3 V
DAC Active and Excluding Load Current
VIH = VDD and VIL = GND
See Figure 6
VIH = VDD and VIL = GND
See Figure 18
t1
t2
CS
WR
D7-D0
t3
t4
t5
LDAC
t6
t7
t8
CLR
Figure 1. Timing Diagram for Parallel Data Write
–2–
REV. 0
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