AD7818ARMZ 查看數據表（PDF） - Analog Devices
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AD7818ARMZ Datasheet PDF : 20 Pages
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Data Sheet
AD7817/AD7818
POWER vs. THROUGHPUT
Superior power performance can be achieved by using the
automatic power-down (Mode 2) at the end of a conversion
(see the Operating Modes section).
tPOWER-UP tCONVERT
2µs
8µs
CONVST
BUSY
tCYCLE
100µs @ 10kSPS
Figure 19. Automatic Power-Down
Figure 19 shows how the automatic power-down is implemented to
achieve the optimum power performance from the AD7817 and
AD7818. The devices operate in Mode 2, and the duration of
CONVST pulse is set equal to the power-up time (2 µs). As the
throughput rate of the device is reduced, the device remains in
its power-down state longer, and the average power consumption
over time drops accordingly.
For example, if the AD7817 operates in continuous sampling
mode with a throughput rate of 10 kSPS, the power consumption
is calculated as follows. The power dissipation during normal
operation is 4.8 mW, VDD = 3 V. If the power-up time is 2 µs,
and the conversion time is 9 µs, the AD7817 can typically dissipate
4.8 mW for 11 µs (worst case) during each conversion cycle. If
the throughput rate is 10 kSPS, the cycle time is 100 µs, and
the power dissipated while powered up during each cycle is
(11/100) × (4.8 mW) = 528 µW typical. Power dissipated while
powered down during each cycle is (89/100) × (3 V × 2 µA) =
5.34 µW typ. Overall power dissipated is 528 µW + 5.34 µW =
533 µW.
10
1
0.1
0.01
0
10
20
30
40
50
60
70
80
THROUGHPUT (kHz)
Figure 20. Power vs. Throughput Rate
AD7817 SERIAL INTERFACE
The serial interface on the AD7817 is a 5-wire interface that has
read and write capabilities, with data being read from the output
register via the DOUT line and data being written to the control
register via the DIN line. The AD7817 operates in slave mode
and requires an externally applied serial clock to the SCLK input
to access data from the data register or write to the control byte.
The RD/WR line is used to determine whether data is being
written to or read from the AD7817. When data is being written
to the AD7817, the RD/WR line is set logic low, and when data
is being read from the part, the RD/WR line is set logic high
(see Figure 21). The serial interface on the AD7817 is designed
to allow the part to be interfaced to systems that provide a serial
clock that is synchronized to the serial data, such as the 80C51,
87C51, 68HC11, 68HC05, and PIC16Cxx microcontrollers.
CS
RD/WR
SCLK
DIN
DOUT
t4
t10
t5
1
2
3
t6
t7
DB7 DB6 DB5
t8
7
8
t9
DB1 DB0
CONTROL BYTE
t11
1
2
3
t12
t13
DB9
DB8
DB7
Figure 21. AD7817 Serial Interface Timing Diagram
9
10
DB1
t14b
t14a
DB0
Rev. D | Page 17 of 20
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