EVAL-AD7858CB 查看數據表（PDF） - Analog Devices

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EVAL-AD7858CB

3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC

Analog Devices 

TYPICAL TIMING DIAGRAMS

Figures 2 and 3 show typical read and write timing diagrams for

serial Interface Mode 2. The reading and writing occurs after

conversion in Figure 2, and during conversion in Figure 3. To

attain the maximum sample rate of 100 kHz (AD7858L) or

200 kHz (AD7858), reading and writing must be performed

during conversion as in Figure 3. At least 400 ns acquisition

time must be allowed (the time from the falling edge of BUSY

to the next rising edge of CONVST) before the next conversion

begins to ensure that the part is settled to the 12-bit level. If the

user does not want to provide the CONVST signal, the conver-

sion can be initiated in software by writing to the control register.

AD7858/AD7858L

1.6mA IOL

TO

OUTPUT

PIN

CL

100pF

200␮A IOH

+2.1V

Figure 1. Load Circuit for Digital Output Timing

Specifications

CONVST (I/P)

t2

BUSY (O/P)

tCONVERT = 4.6␮s MAX, 10␮s MAX FOR L VERSION

t1 = 100ns MIN, t4 = 50/90ns MAX 5V/3V, t7 = 40/60ns MIN 5V/3V

t1

tCONVERT

SYNC (I/P)

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

t3

t4

THREE-STATE

1

t6

DB15

t7

t8

DB15

t9

5

6

t6 t10

DB11

t11

16

t12

DB0

THREE-

STATE

DB11

DB0

Figure 2. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)

t1

CONVST (I/P)

t2

BUSY (O/P)

tCONVERT = 4.6␮s MAX, 10␮s MAX FOR L VERSION

t1 = 100ns MIN, t4 = 50/90ns MAX 5V/3V, t7 = 40/60ns MIN 5V/3V

tCONVERT

SYNC (I/P)

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

t3

1

t4

THREE-STATE

t6

DB15

t7

t8

DB15

t9

5

6

t6 t10

DB11

t11

16

t12

DB0

THREE-

STATE

DB11

DB0

Figure 3. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)

REV. B

–5–

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