EVAL-AD7887CB 查看數據表（PDF） - Analog Devices
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EVAL-AD7887CB
Analog Devices
EVAL-AD7887CB Datasheet PDF : 24 Pages
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AD7887
TIMING SPECIFICATIONS1
Table 2.
Parameter
fSCLK 2
tCONVERT
tACQ
t1
t2 3
t33
t4
t5
t6
t7
t8 4
t9
Limit at TMIN, TMAX
(A, B Versions)
4.75 V to 5.25 V
2.7 V to 3.6 V
2
2
14.5 × tSCLK
1.5 × tSCLK
10
14.5 × tSCLK
1.5 × tSCLK
10
30
60
75
100
20
20
20
20
0.4 × tSCLK
0.4 × tSCLK
80
0.4 × tSCLK
0.4 × tSCLK
80
5
5
Unit
MHz max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
μs typ
Description
Throughput time = tCONVERT + tACQ = 16 tSCLK
CS to SCLK setup time
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
Data setup time prior to SCLK rising edge
Data valid to SCLK hold time
SCLK high pulse width
SCLK low pulse width
CS rising edge to DOUT high impedance
Power-up time from shutdown
1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
200µA
IOL
TO
OUTPUT
PIN CL
50pF
1.6V
200µA
IOH
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. D | Page 5 of 24
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