AD7991 查看數據表（PDF） - Analog Devices
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AD7991 Datasheet PDF : 28 Pages
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AD7991/AD7995/AD7999
Parameter
LOGIC INPUTS (SDA, SCL)
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current, IIN
Input Capacitance, CIN7
Input Hysteresis, VHYST
LOGIC OUTPUTS (OPEN
DRAIN)
Output Low Voltage, VOL
Floating-State Leakage
Current
Floating-State Output
Capacitance7
Output Coding
THROUGHPUT RATE
POWER REQUIREMENTS3
A Version2
Min Typ Max
0.7 (VDD)
0.3 (VDD)
±1
10
0.1 (VDD)
0.4
0.6
±1
10
Straight (natural) binary
18×(1/fSCL)
17.5×(1/fSCL)
+ 2 μs
Y Version
Min Typ Max
0.7 (VDD)
0.9 (VDD)
0.1 (VDD)
0.3 (VDD)
0.1 (VDD)
±1
10
0.4
0.6
±1
10
Straight (natural) binary
18×(1/fSCL)
17.5×(1/fSCL)
+ 2 μs
Unit
V
V
V
V
μA
pF
V
V
V
μA
pF
VDD
2.7
IDD
ADC Operating,
Interface Active
(Fully Operational)
Power-Down,
Interface Active8
Power-Down ,
Interface Inactive8
Power Dissipation
ADC Operating,
Interface Active
(Fully Operational)
Power-Down,
Interface Active8
Power-Down ,
Interface Inactive8
5.5
2.7
0.25
0.26
1
0.83
0.86
3.3
5.5
V
0.09/0.25 mA
0.25/0.8
mA
0.07/0.16 mA
0.26/0.85 mA
1/1.6
μA
0.3/1.38
mW
0.83/4.4
mW
0.24/0.88 mW
0.86/4.68 mW
3.3/8.8
μW
Test Conditions/Comments
VDD = 2.7 V to 5.5 V
VDD = 2.35 V to 2.7 V
VDD = 2.7 V to 5.5 V
VDD = 2.35 V to 2.7 V
VIN = 0 V or VDD
ISINK = 3 mA
ISINK = 6 mA
fSCL ≤ 1.7 MHz; see the Serial Interface section
fSCL > 1.7 MHz; see the Serial Interface section
VREF = VDD; for fSCL = 3.4 MHz,
clock stretching is implemented
Digital inputs = 0 V or VDD
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V
1 Functional from VDD = 2.35 V.
2 A Version tested at VDD=3.3 V and fSCL= 3.4 MHz. Functionality tested at fSCL = 400 kHz.
3 Sample delay and bit trial delay enabled, t1 = t2 = 0.5/fSCL.
4 For fSCL up to 400 kHz, clock stretching is not implemented. Above fSCL = 400 kHz, clock stretching is implemented.
5 See the Terminology section.
6 For fSCL ≤ 1.7 MHz, clock stretching is not implemented; for fSCL > 1.7 MHz, clock stretching is implemented.
7 Guaranteed by initial characterization.
8 See the Reading from the AD7991/AD7995/AD7999 section.
Rev. A | Page 8 of 28
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