AD7998 查看數據表（PDF） - Analog Devices
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AD7998 Datasheet PDF : 32 Pages
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AD7997/AD7998
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
AGND 1
20 AGND
VDD
AGND
AGND
VDD
2 AD7997/ 19 SCL
3 AD7998 18 SDA
4 TOP VIEW 17 ALERT/BUSY
5 (Not to Scale) 16 CONVST
REFIN 6
VIN1 7
VIN3 8
VIN5 9
VIN7 10
15 AS
14 VIN2
13 VIN4
12 VIN6
11 VIN8
Table 5. Pin Function Descriptions
Figure 3. AD7998/AD7997 Pin Configuration
Pin No. Mnemonic
Function
1, 3,
AGND
4, 20
Analog Ground. Ground reference point for all circuitry on the AD7997/AD7998. All analog input signals should be
referred to this AGND voltage.
2, 5
VDD
Power Supply Input. The VDD range for the AD7997/AD7998 is from 2.7 V to 5.5 V.
6
REFIN
Voltage Reference Input. The external reference for the AD7997/AD7998 should be applied to this input pin. The
voltage range for the external reference is 1.2 V to VDD. A 0.1 µF and 1 µF capacitors should be placed between REFIN
and AGND. See Typical Connection Diagram.
7
VIN1
8
VIN3
9
VIN5
Analog Input 1. Single-ended analog input channel. The input range is 0 V to REFIN.
Analog Input 3. Single-ended analog input channel. The input range is 0 V to REFIN.
Analog Input 5. Single-ended analog input channel. The input range is 0 V to REFIN.
10
VIN7
11
VIN8
12
VIN6
Analog Input 7. Single-ended analog input channel. The input range is 0 V to REFIN.
Analog Input 8. Single-ended analog input channel. The input range is 0 V to REFIN.
Analog Input 6. Single-ended analog input channel. The input range is 0 V to REFIN.
13
VIN4
14
VIN2
15
AS
Analog Input 4. Single-ended analog input channel. The input range is 0 V to REFIN.
Analog Input 2. Single-ended analog input channel. The input range is 0 V to REFIN.
Logic Input. Address select input that selects one of three I2C addresses for the AD7997/AD7998, as shown in Table 6.
The device address depends on the voltage applied to this pin.
16
CONVST
Logic Input Signal. Convert start signal. This is an edge-triggered logic input. The rising edge of this signal powers up
the part. The power-up time for the part is 1 µs. The falling edge of CONVST places the track/hold into hold mode and
initiates a conversion. A power-up time of at least 1 µs must be allowed for the CONVST high pulse; otherwise, the
conversion result is invalid (see the Modes of Operation section).
17
ALERT/BUSY Digital Output. Selectable as an ALERT or BUSY output function. When configured as an ALERT, this pin acts as an out-
of-range indicator and, if enabled, becomes active when the conversion result violates the DATAHIGH or DATALOW
register values. See the Limit Registers section. When configured as a BUSY output, this pin becomes active when a
conversion is in progress. Open-drain output.
18
SDA
Digital I/O. Serial bus bidirectional data. Open-drain output. External pull-up resistor required.
19
SCL
Digital Input. Serial bus clock. Open-drain input. External pull-up resistor required.
Table 6. I2C Address Selection
Part Number
AD7997-0
AD7997-0
AD7997-1
AD7997-1
AD7997-x1
AD7998-0
AD7998-0
AD7998-1
AD7998-1
AD7998-x1
AS Pin
AGND
VDD
AGND
VDD
Float
AGND
VDD
AGND
VDD
Float
I2C Address
010 0001
010 0010
010 0011
010 0100
010 0000
010 0001
010 0010
010 0011
010 0100
010 0000
1 If the AS pin is left floating on any of the AD7997/AD7998 parts, the device address is 010 0000.
Rev. 0 | Page 10 of 32
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