AD7997 查看數據表（PDF） - Analog Devices
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AD7997 Datasheet PDF : 32 Pages
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AD7997/AD7998
Parameter
LOGIC INPUTS (CONVST)
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current, IIN
Input Capacitance, CIN3
LOGIC OUTPUTS (OPEN-DRAIN)
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
CONVERSION RATE
Conversion Time
Throughput Rate
Mode 1 (Reading after the Conversion)
Mode 2
POWER REQUIREMENTS
VDD
IDD
Power-Down Mode, Interface Inactive
Power-Down Mode, Interface Active
Operating, Interface Inactive
Operating, Interface Active
Mode 3 (I2C Inactive, TCONVERT x 32)
Power Dissipation
Fully Operational
Operating, Interface Active
Power Down, Interface Inactive
B Version
Unit
Test Conditions/Comments
2.4
V min
VDD = 5 V
2.0
V min
VDD = 3 V
0.8
V max
VDD = 5 V
0.4
V max
VDD = 3 V
±1
µA max
VIN = 0 V or VDD
10
pF max
0.4
V max
0.6
V max
±1
µA max
10
pF max
Straight (Natural) Binary
2
µs typ
ISINK = 3 mA
ISINK = 6 mA
See the Modes of Operation section
5
kSPS typ
fSCL = 100 kHz
21
kSPS typ
fSCL = 400 kHz
121
kSPS typ
fSCL = 3.4 MHz
5.5
kSPS typ
fSCL = 100 kHz
22
kSPS typ
fSCL = 400 kHz
147
kSPS typ
fSCL = 3.4 MHz, 188 kSPS typ @ 5 V
2.7/5.5
1/2
0.07/0.3
0.3/0.6
0.06/0.1
0.3/0.6
0.15/0.4
0.6/1.1
0.7/1.4
0.7/1.5
V min/max
µA max
mA max
mA max
mA max
mA max
mA max
mA max
mA typ
mA max
Digital inputs = 0 V or VDD
VDD = 3.3 V/5.5 V
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 1
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 2
VDD = 3.3 V/5.5 V
0.495/2.2
1.98/6.05
2.31/7.7
3.3/11
mW max
mW max
mW typ
µW max
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 1
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 2
VDD = 3.3 V/5.5 V
1 Max/min ac dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I2C Hs-Mode SCL frequencies. Specifications
outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.
2 See the Terminology section.
3 Guaranteed by initial characterization.
Rev. 0 | Page 4 of 32
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