AD8229HDZ 查看數據表（PDF） - Analog Devices

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AD8229HDZ

1 nV/√Hz Low Noise 210°C Instrumentation Amplifier

Analog Devices 

AD8229

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 6

Predicted Lifetime vs. Operating Temperature ........................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

REVISION HISTORY

2/12—Rev. A to Rev. B

Added 8-Lead SOIC ...........................................................Universal

Changes to Features Section and General Description Section...... 1

Changes to Table 1............................................................................ 3

Changes to Table 2, Thermal Resistance Section, and Table 3 ... 6

Updated Outline Dimensions ....................................................... 21

Changes to Ordering Guide .......................................................... 21

9/11—Rev. 0 to Rev. A

Changes to Features Section and General Description Section...... 1

Changes to Table 2............................................................................ 6

Added Predicted Lifetime vs. Operating Temperature Section and

Figure 3; Renumbered Sequentially .............................................. 6

Changes to Figure 18 and Figure 19............................................. 10

Changes to Figure 24 to Figure 28................................................ 11

Changes to Figure 29 and Figure 30............................................. 12

Changes to Figure 48...................................................................... 15

Changes to Figure 56...................................................................... 17

Changes to Power Supplies Section.............................................. 18

1/11—Revision 0: Initial Version

Data Sheet

Theory of Operation ...................................................................... 17

Architecture ................................................................................ 17

Gain Selection ............................................................................. 17

Reference Terminal .................................................................... 17

Input Voltage Range................................................................... 18

Layout .......................................................................................... 18

Input Bias Current Return Path ............................................... 19

Input Protection ......................................................................... 19

Radio Frequency Interference (RFI)........................................ 19

Calculating the Noise of the Input Stage................................. 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 21

Rev. B | Page 2 of 24

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