AD8567ARU-REEL 查看數據表（PDF） - Analog Devices
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AD8567ARU-REEL Datasheet PDF : 16 Pages
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THEORY OF OPERATION
The AD856x family is designed to drive large capacitive loads in
LCD applications. It has high output current drive, rail-to-rail
input/output operation, and is powered from a single 16 V
supply. It is also intended for other applications where low
distortion and high output current drive are needed.
Figure 28 illustrates a simplified equivalent circuit for the
AD856x. The rail-to-rail bipolar input stage is composed of two
PNP differential pairs, Q4 to Q5 and Q10 to Q11, operating in
series with diode protection networks, D1 to D2. Diode network
D1 to D2 serves as protection against large transients for Q4 to
Q5 to accommodate rail-to-rail input swing. D5 to D6 protect
Q10 to Q11 against Zenering. In normal operation, Q10 to Q11
are off and their input stage is buffered from the operational
amplifier inputs by Q6 to D3 and Q8 to D4. Operation of the
input stage is best understood as a function of applied
common-mode voltage: when the inputs of the AD856x are
biased midway between the supplies, the differential signal path
gain is controlled by resistive loads (via R9, R10) Q4 to Q5. As
the input common-mode level is reduced toward the negative
supply (VNEG or GND), the input transistor current sources, I1
and I2, are forced into saturation, thereby forcing the Q6 to D3
and Q8 to D4 networks into cutoff. However, Q4 to Q5 remain
active, providing input stage gain. Inversely, when common-
mode input voltage is increased toward the positive supply, Q4
to Q5 are driven into cutoff, Q3 is driven into saturation, and
Q4 becomes active, providing bias to the Q10 to Q11 differential
pair. The point at which Q10 to Q11 differential pair becomes
active is approximately equal to (VPOS − 1 V).
VPOS
R1
Q3
Q4
BIAS LINE
Q6
V+
D1
R3
C1
Q4
D3
R5
R6
C2
Q10
Q11
D5
D2
R4
Q5
Q8
V–
D4
I1
R9
D6
I2
FOLDED
CASCADE
R10
VNEG
Figure 28. AD856x Equivalent Input Circuit
AD8565/AD8566/AD8567
The benefit of this type of input stage is low bias current. The
input bias current is the sum of base currents of Q4 to Q5 and
Q6 to Q8 over the range from (VNEG + 1 V) to (VPOS − 1 V).
Outside of this range, input bias current is dominated by the
sum of base currents of Q10 to Q11 for input signals close to
VNEG and of Q6 to Q8 (Q10 to Q11) for signals close to VPOS.
From this type of design, the input bias current of AD856x not
only exhibits different amplitude but also exhibits different
polarities. Figure 29 provides the characteristics of the input
bias current vs. the common-mode voltage. It is important to
keep in mind that the source impedances driving the AD856x
inputs are balanced for optimum dc and ac performance.
1000
800
600
VS = 16V
TA = 25°C
400
200
0
–200
–400
–600
–800
–1000
0
2
4
6
8
10
12
14
16
INPUT COMMON-MODE VOLTAGE (V)
Figure 29. AD856x Input Bias Current vs. Common-Mode Voltage
To achieve rail-to-rail output performance, the AD856x design
uses a complementary common-source (or gmRL) output. This
configuration allows output voltages to approach the power
supply rails, particularly if the output transistors are allowed to
enter the triode region on extremes of signal swing, which are
limited by VGS, the transistor sizes, and output load current. In
addition, this type of output stage exhibits voltage gain in an
open-loop gain configuration. The amount of gain depends on
the total load resistance at the output of the AD856x.
INPUT OVERVOLTAGE PROTECTION
As with any semiconductor device, whenever the input exceeds
either supply voltages, attention needs to be paid to the input
overvoltage characteristics. As an overvoltage occurs, the amplifier
could be damaged, depending on the voltage level and the
magnitude of the fault current. When the input voltage exceeds
either supply by more than 0.6 V, internal pn junctions allow
current to flow from the input to the supplies.
Rev. D | Page 9 of 16
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