AD8555ARZ-REEL71 查看數據表（PDF） - Analog Devices

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AD8555ARZ-REEL71

Zero-Drift, Digitally Programmable Sensor Signal Amplifier

Analog Devices 

AD8555

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VDD 1

8 VSS

FILT/DIGOUT 2 AD8555 7 VOUT

TOP VIEW

DIGIN 3 (Not to Scale) 6 VCLAMP

VNEG 4

5 VPOS

Figure 2. 8-Lead SOIC (Not Drawn to Scale)

NC 1

FILT/DIGOUT 2

NC 3

DIGIN 4

PIN 1

INDICATOR

AD8555

TOP VIEW

12 VOUT

11 NC

10 VCLAMP

9 NC

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PAD MUST BE CONNECTED

TO AVSS (PIN 14).

Figure 3. 16-Lead LFCSP (Not Drawn to Scale)

Table 5. Pin Configuration

SOIC

Pin No. Mnemonic Pin No.

N/A

0

1

VDD

N/A

2

FILT/DIGOUT 2

LFCSP

Mnemonic

EPAD

N/A

FILTDIGOUT

3

DIGIN

4

VNEG

5

VPOS

6

VCLAMP

7

VOUT

8

VSS

N/A

N/A

N/A

N/A

N/A

N/A

4

DIGIN

6

VNEG

8

VPOS

10

VCLAMP

12

VOUT

N/A

13, 14

15, 16

1, 3, 5, 7, 9, 11

N/A

DVSS, AVSS

DVDD, AVDD

NC

Description

Exposed Pad. The exposed pad must be connected to AVSS (Pin 14)

Positive Supply Voltage.

Unbuffered Amplifier Output In Series with a Resistor RF. Adding a capacitor

between FILT and VDD or VSS implements a low-pass filtering function. In

read mode, this pin functions as a digital output.

Digital Input.

Negative Amplifier Input (Inverting Input).

Positive Amplifier Input (Noninverting Input).

Set Clamp Voltage at Output.

Buffered Amplifier Output. Buffered version of the signal at the FILT/DIGOUT

pin. In read mode, VOUT is a buffered digital output.

Negative Supply Voltage.

Negative Supply Voltage.

Positive Supply Voltage.

Do Not Connect.

Rev. A | Page 8 of 28

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