AD9139(Rev0) 查看數據表（PDF） - Analog Devices
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AD9139 Datasheet PDF : 56 Pages
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AD9139
SERIAL PORT OPERATION
The serial port is a flexible, synchronous serial communications
port that allows easy interfacing to many industry standard micro-
controllers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including both the
Motorola SPI and Intel® SSR protocols. The interface allows
read/write access to all registers that configure the AD9139.
MSB first or LSB first transfer formats are supported. The serial
port interface is a 3-wire only interface. The input and output
share a single input/output (SDIO) pin.
54 CS
SPI
PORT 53 SCLK
52 SDIO
Figure 23. Serial Port Interface Pins
There are two phases to a communication cycle with the AD9139.
Phase 1 is the instruction cycle (the writing of an instruction
byte into the device), coincident with the first 16 SCLK rising
edges. The instruction word provides the serial port controller
with information regarding the data transfer cycle, Phase 2, of
the communication cycle. The Phase 1 instruction word defines
whether the upcoming data transfer is a read or write, together
with the starting register address for the following data transfer.
A logic high on the CS pin, followed by a logic low, resets the
serial port timing to the initial state of the instruction cycle.
From this state, the next 16 rising SCLK edges represent the
instruction bits of the current I/O operation.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the device and
the system controller. Phase 2 of the communication cycle is a
transfer of one data byte. Registers change immediately upon
writing to the last bit of each transfer byte.
DATA FORMAT
The instruction byte contains the information shown in Table 9.
Table 9. Serial Port Instruction Word
I15 (MSB)
I[14:0]
R/W
A[14:0]
R/W (Bit 15 of the instruction word) determines whether a read
or a write data transfer occurs after the instruction word write.
Logic 1 indicates a read operation, and Logic 0 indicates a write
operation.
Data Sheet
A14 to A0 (Bit 14 to Bit 0 of the instruction word) determine
the register that is accessed during the data transfer portion of
the communication cycle. For multibyte transfers, A14 is the
starting address; the device generates the remaining register
addresses based on the SPI_LSB_FIRST bit.
SERIAL PORT PIN DESCRIPTIONS
Serial Clock (SCLK)
The serial clock pin, SCLK, synchronizes data to and from the
device and runs the internal state machines. The maximum
frequency of SCLK is 40 MHz. All data input is read on the rising
edge of SCLK. All data is driven out on the falling edge of SCLK.
Chip Select (CS)
CS is an active low input that starts and gates a communication
cycle. It allows the use of multiple devices on the same serial
communications line. The SDIO pin enters a high impedance
state when the CS input is high. During the communication
cycle, CS remains low.
Serial Data I/O (SDIO)
The SDIO pin is a bidirectional data line.
SERIAL PORT OPTIONS
The serial port supports both MSB first and LSB first data
formats; the SPI_LSB_FIRST bit (Register 0x00, Bit 6) controls
this functionality. The default is MSB first (SPI_LSB_FIRST = 0).
When SPI_LSB_FIRST = 0 (MSB first), the instruction and data
bits must be written from MSB to LSB. Multibyte data transfers
in MSB first format start with an instruction word that includes the
register address of the most significant data byte. Subsequent data
bytes must follow from high address to low address. In MSB first
mode, the serial port internal word address generator decrements
for each data byte of the multibyte communication cycle.
When SPI_LSB_FIRST = 1 (LSB first), the instruction and data
bits must be written from LSB to MSB. Multibyte data transfers
in LSB first format start with an instruction word that includes the
register address of the least significant data byte. Subsequent data
bytes must follow from low address to high address. In LSB first
mode, the serial port internal word address generator increments
for each data byte of the multibyte communication cycle.
When the MSB first mode is active, the serial port controller
data address decrements from the data address written toward
0x00 for multibyte I/O operations. If the LSB first mode is
active, the serial port controller data address increments from
the data address written toward 0xFF for multibyte I/O
operations.
Rev. 0 | Page 16 of 56
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