AD9139(Rev0) 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

AD9139
(Rev.:Rev0)

16-Bit, 1600 MSPS, TxDAC+ Digital-to-Analog Converter

Analog Devices 

AD9139

DATA INTERFACE

LVDS INPUT DATA PORTS

The AD9139 has a 16-bit LVDS bus that accepts 16-bit data

either in word wide (16-bit) or byte wide (8-bit) formats. In the

word wide interface mode, the data is sent over the entire 16-bit

data bus. In the byte wide interface mode, the data is sent over

the lower 8-bit (D7 to D0) LVDS bus. Table 10 lists the pin

assignment of the bus and the SPI register configuration for

each mode.

Table 10. LVDS Input Data Modes

Input Data

Interface Mode Width

SPI Register Configuration

Word

D15 to D0

Register 0x26, Bit 0 = 0

Byte

D7 to D0

Register 0x26, Bit 0 = 1

WORD INTERFACE MODE

In word mode, the digital clock input (DCI) signal is a reference

bit that generates a double data rate (DDR) data sampling clock.

Time align the DCI signal with the data.

AD9139 WORD MODE

INPUT DATA[15:0]

S0

S1

S2

S3

DCI

Figure 28. AD9139 Timing Diagram for Word Mode

BYTE INTERFACE MODE

In byte mode, the required sequence of the input data stream is

S0[15:8], S0[7:0], S1[15:8], S1[7:0], and so forth. A frame signal

is required to align the order of input data bytes properly. Time

align both the DCI signal and frame signal with the data. The

rising edge of the frame indicates the start of the sequence. The

frame can be either a one shot or periodical signal as long as its

first rising edge is correctly captured by the device. For a one

shot frame, the frame pulse must be held at high for at least one

DCI cycle. For a periodical frame, the frequency must be

fDCI/(2 × n)

where n is a positive integer, that is, 1, 2, 3, …

Figure 29 is an example of signal timing in byte mode.

AD9139 WORD MODE

INPUT DATA[7:0]

S0[15:8]

S0[7:0]

S1[15:8]

S1[7:0]

DCI

FRAME

Figure 29. Timing Diagram for Byte Mode

Data Sheet

DATA INTERFACE CONFIGURATION OPTIONS

To provide more flexibility for the data interface, additional

options are listed in Table 11.

Table 11. Data Interface Configuration Options

Register 0x26, Bit 7 Description

DATA_FORMAT

Select between binary and twos

complement formats.

DLL INTERFACE MODE

A source synchronous LVDS interface is used between the data

host and the AD9139 to achieve high data rates while simplifying

the interface. The FPGA or ASIC feeds the AD9139 with 16-bit

input data. Together with the input data, the FPGA or ASIC

provides a DDR DCI.

A delay locked loop (DLL) circuit, designed to operate with

DCI clock rates between 250 MHz and 575 MHz, generates a

phase shifted version of the DCI signal, called a data sampling

clock (DSC), to register the input data on both the rising and

falling edges.

As shown in Figure 31, the DCI clock edges must be coincident

with the data bit transitions with minimum skew and jitter. The

nominal sampling point of the input data occurs in the middle

of the DCI clock edges because this point corresponds to the

center of the data eye. This is also equivalent to a nominal phase

shift of 90°of the DCI clock.

The data timing requirements are defined by a data valid

window (DVW) that is dependent on the data clock input skew,

input data jitter, and the variations of the DLL delay line across

delay settings. The DVW is defined as

DVW = tDATA PERIOD − tDATA SKEW − tDATA JITTER

The available margin for data interface timing is given by

tMARGIN = DVW − (tS + tH)

The difference of the setup and hold times, which is also called

the keep out window, or KOW, is the area where data transitions

are prohibited. The timing margin allows the user to set the

DLL delay, as shown in Figure 30.

Rev. 0 | Page 18 of 56

Share Link: