AD9257(Rev0) 查看數據表（PDF） - Analog Devices
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AD9257
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD9257 Datasheet PDF : 40 Pages
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AD9257
Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4.
Parameter1, 2
CLOCK3
Input Clock Rate
Conversion Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS3
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO)
DCO Propagation Delay (tCPD)4
DCO to Data Delay (tDATA)4
DCO to FCO Delay (tFRAME)4
Data to Data Skew
(tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)5
Pipeline Latency
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
25°C
25°C
25°C
Min
10
10
1.5
(tSAMPLE/28) − 300
(tSAMPLE/28) − 300
Typ
12.5/7.69
12.5/7.69
2.3
300
300
2.3
tFCO + (tSAMPLE/28)
(tSAMPLE/28)
(tSAMPLE/28)
±50
35
375
16
1
0.1
1
Max
520
40/65
3.1
(tSAMPLE/28) + 300
(tSAMPLE/28) + 300
±200
Unit
MHz
MSPS
ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
μs
μs
Clock
cycles
ns
ps rms
Clock
cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Measured on standard FR-4 material.
3 Can be adjusted via the SPI.
4 tSAMPLE/28 is based on the number of bits divided by 2 because the delays are based on half duty cycles. tSAMPLE = 1/fS.
5 Wake-up time is defined as the time required to return to normal operation from power-down mode.
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
Description
Limit Unit
SYNC to rising edge of CLK+ setup time
0.24 ns typ
SYNC to rising edge of CLK+ hold time
0.40 ns typ
See Figure 61
Setup time between the data and the rising edge of SCLK
2
ns min
Hold time between the data and the rising edge of SCLK
2
ns min
Period of the SCLK
40
ns min
Setup time between CSB and SCLK
2
ns min
Hold time between CSB and SCLK
2
ns min
SCLK pulse width high
10
ns min
SCLK pulse width low
10
ns min
Time required for the SDIO pin to switch from an input to an output 10
relative to the SCLK falling edge (not shown in Figure 61)
ns min
Time required for the SDIO pin to switch from an output to an input 10
relative to the SCLK rising edge (not shown in Figure 61)
ns min
Rev. 0 | Page 6 of 40
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