AD9257 查看數據表（PDF） - Analog Devices

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AD9257

Octal, 14-Bit, 40/65 MSPS, Serial LVDS, 1.8 V Analog-to-Digital Converter

Analog Devices 

Data Sheet

Timing Diagrams

VIN± x

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

D– x

D+ x

VIN± x

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

D– x

D+ x

AD9257

N–1

tA

tEH

tCPD

N

tEL

tFCO

tFRAME

tPD

tDATA

MSB D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D12

N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16

Figure 2. Word-Wise DDR,1× Frame, 14-Bit Output Mode (Default)

N–1

tA

tEH

N

tEL

tCPD

tFCO

tFRAME

tPD

tDATA

MSB D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0 MSB D10

N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16

Figure 3. Word-Wise DDR, 1× Frame, 12-Bit Output Mode

CLK+

SYNC

tSSYNC

tHSYNC

Figure 4. SYNC Input Timing Requirements

Rev. A | Page 7 of 40

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