AD9258 查看數據表（PDF） - Analog Devices

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AD9258

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)

Analog Devices 

AD9258

TIMING SPECIFICATIONS

Table 5.

Parameter

SYNC TIMING REQUIREMENTS

tSSYNC

tHSYNC

SPI TIMING REQUIREMENTS

tDS

tDH

tCLK

tS

tH

tHIGH

tLOW

tEN_SDIO

tDIS_SDIO

Conditions

SYNC to rising edge of CLK+ setup time

SYNC to rising edge of CLK+ hold time

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

SCLK pulse width high

SCLK pulse width low

Time required for the SDIO pin to switch from an input to an output relative to the SCLK

falling edge

Time required for the SDIO pin to switch from an output to an input relative to the SCLK

rising edge

Limit

0.30 ns typ

0.40 ns typ

2 ns min

2 ns min

40 ns min

2 ns min

2 ns min

10 ns min

10 ns min

10 ns min

10 ns min

Timing Diagrams

VIN

CLK+

CLK–

DCOA/DCOB

CH A/CH B DATA

N–1

tCH

tA

N

N+1

tCLK

N+2

N+3

N+4

N+5

tDCO

tSKEW

N – 13

N – 12

N – 11

N – 10

tPD

Figure 2. CMOS Default Output Mode Data Output Timing

N–9

N–8

VIN

CLK+

CLK–

DCOA/DCOB

CH A/CH B DATA

N–1

tCH

tA

N

N+1

tCLK

N+2

N+3

N+4

N+5

tDCO

tSKEW

tPD

CH A CH B CH A CH B CH A CH B

N – 12 N – 12 N – 11 N – 11 N – 10 N – 10

CH A

N–9

CH B

N–9

CH A

N–8

Figure 3. CMOS Interleaved Output Mode Data Output Timing

Rev. A | Page 10 of 44

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