AD9259-50EB 查看數據表（PDF） - Analog Devices
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AD9259-50EB Datasheet PDF : 52 Pages
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AD9259
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
Parameter1
CLOCK2
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS2
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO)
DCO Propagation Delay (tCPD)3
DCO to Data Delay (tDATA)3
DCO to FCO Delay (tFRAME)3
Data to Data Skew
(tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby)
Wake-Up Time (Power Down)
Pipeline Latency
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
Min
50
2.0
2.0
(tSAMPLE/28) − 300
(tSAMPLE/28) − 300
25°C
25°C
25°C
AD9259-50
Typ
Max
10
10
2.7
300
300
2.7
tFCO +
(tSAMPLE/28)
(tSAMPLE/28)
(tSAMPLE/28)
±50
600
375
10
10
3.5
3.5
(tSAMPLE/28) + 300
(tSAMPLE/28) + 300
±150
500
<1
2
Unit
MSPS
MSPS
ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
ns
μs
CLK
cycles
ps
ps rms
CLK
cycles
1 See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.
2 Can be adjusted via the SPI interface.
3 tSAMPLE/28 is based on the number of bits multiplied by 2; delays are based on half duty cycles.
Rev. 0 | Page 6 of 52
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