AD9286 查看數據表（PDF） - Analog Devices
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AD9286 Datasheet PDF : 27 Pages
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AD9286
Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
CLK Period (tCLK)
CLK Pulse Width High (tCH)
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)
DCO to Data Skew (tSKEW)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time1
OUT-OF-RANGE RECOVERY TIME
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
Typ
Max
Unit
60
500
MHz
2
Ns
1
Ns
3.7
ns
3.7
ns
−280
−60
100
ps
11
Cycles
1.0
ns
0.1
ps rms
500
μs
4
Cycles
1 Wake-up time is dependent on the value of the decoupling capacitors.
SPI TIMING SPECIFICATIONS
Table 5.
Parameter
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
Description
Min
Setup time between the data and the rising edge of SCLK 2
Hold time between the data and the rising edge of SCLK 2
Period of the SCLK
40
Setup time between CSB and SCLK
2
Hold time between CSB and SCLK
2
SCLK pulse width high
10
SCLK pulse width low
10
Time required for the SDIO pin to switch from an input 10
to an output relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output 10
to an input relative to the SCLK rising edge
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Timing Diagrams
M–1
VIN1+, VIN1–
tA
N–2
VIN2+, VIN2–
N–1
CLK+
CLK–
tCH
tDCO
M+4
M
M+5
M+3
M+1
M+2
N+3
N+4
N
tA
tCLK
N+1
N+2
DCO+, DCO–
DATA
tSKEW
M – 11 N – 11 M – 10 N – 10 M – 9 N – 9 M – 8 N – 8 M – 7
tPD
Figure 2. Output Timing Diagram, Sample Mode = Interleaved (Default)
Rev. C | Page 6 of 27
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