AD9381 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
AD9381 Datasheet PDF : 44 Pages
| |||
AD9381
Parameter
IDVDD Supply Current (Typical
Pattern)1, 4
IPVDD Supply Current (Typical
Pattern)1
Power-Down Supply Current (IPD)
AC SPECIFICATIONS
Intrapair (+ to −) Differential Input
Skew (TDPS)
Channel to Channel Differential
Input Skew (TCCS)
Low-to-High Transition Time for
Data and Controls (DLHT)
Low-to-High Transition Time for
DATACK (DLHT)
High-to-Low Transition Time for
Data and Controls (DHLT)
High-to-Low Transition Time for
DATACK (DHLT)
Clock to Data Skew5 (TSKEW)
Duty Cycle, DATACK5
DATACK Frequency (FCIP)
Test Level Conditions
V
V
VI
IV
IV
IV
Output drive = high;
CL = 10 pF
IV
Output drive = low;
CL = 5 pF
IV
Output drive = high;
CL = 10 pF
IV
Output drive = low;
CL = 5 pF
IV
Output drive = high;
CL = 10 pF
IV
Output drive = low;
CL = 5 pF
IV
Output drive = high;
CL = 10 pF
IV
Output drive = low;
CL = 5 pF
IV
IV
VI
AD9381KSTZ-100
Min
Typ Max
88 110
26 35
130
–0.5
+2.0
45
50
20
1 The typical pattern contains a gray scale area, output drive = high. Worst-case pattern is alternating black and white pixels.
2 The typical pattern contains a gray scale area, output drive = high.
3 Specified current and power values with a worst-case pattern (on/off).
4 DATACK load = 10 pF, data load = 5 pF.
5 Drive strength = high.
AD9381KSTZ-150
Min Typ Max Unit
110 145 mA
30 40 mA
130
mA
360 ps
6
Clock
Period
900 ps
1300 ps
650 ps
1200 ps
850 ps
1250 ps
800 ps
1200 ps
–0.5
+2.0 ns
55 %
150 MHz
Rev. 0 | Page 4 of 44
Share Link: 