AD9389B
Preliminary Technical Data
LFCSP
34
33
Pin No.
LQFP
45
44
Mnemonic
DDCSDA
DDCSCL
Type 1
C2
C2
Description
Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus.
Supports a 5 V CMOS logic level.
Serial Port Data Clock to Receiver. This pin serves as the master clock for the
DDC bus. Supports a 5 V CMOS logic level.
1 I = input, O = output, P = power supply, C = control.
2 For a full description of the 2-wire serial interface and its functionality, obtain documentation by contacting NDA from flatpanel_apps@analog.com.
Rev. PrA | Page 8 of 12