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AD9393 查看數據表(PDF) - Analog Devices

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产品描述 (功能)
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AD9393
ADI
Analog Devices ADI
AD9393 Datasheet PDF : 40 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AD9393
Pin No.
B8
A9
References
D10
Power Supply1
E7, F7
D4, D5
Mnemonic
VSOUT
O/E
FILT
VD
VDD
F9, G9
PVDD
G6, G7
DVDD
C9, C10, D6, D7, D9, E4, GND
E9, E10,
F4, H10, J1, K3, K6, K9
Control
A10
SDA
B10
HDCP
H9
J9
SCL
DDC_SCL
DDC_SDA
F10
G10
Audio Data Outputs
J7
J6
J5
J4
J3
J2
G4
G5
Data Enable
B7
RTERM
J8
MDA
MCL
S/PDIF
I2S0
I2S1
I2S2
I2S3
MCLK
SCLK
LRCLK
DE
RTERM
Description
VSYNC Output Clock (Phase-Aligned with DCLK). Vertical Sync Output. The
separated VSYNC from a composite signal or a direct passthrough of the
VSYNC signal. The polarity of this output can be controlled via the serial bus
bit (Register 0x24[6]).
Odd/Even Field Output for Interlaced Video. This output identifies whether the
current field (in an interlaced signal) is odd or even. The polarity of this signal
is programmable via Register 0x24[4].
Value
VDD
VDD
Connection for External Filter Components for Audio PLL. For proper operation, PVDD
the audio clock generator PLL requires an external filter. Connect the filter
shown in Figure 6 to this pin. For optimal performance, minimize noise and
parasitics on this node. For more information, see the PCB Layout
Recommendations section.
HDMI Terminator Power Supply (3.3 V). These pins supply power to the HDMI
terminators. They should be as quiet and filtered as possible.
Digital Output Power Supply (1.8 V to 3.3 V). A large number of output pins (up
to 27) switching at high speed (up to 80 MHz) generates many power supply
transients (noise). These supply pins are identified separately from the VD pins,
so output noise transferred into the sensitive circuitry can be minimized. If the
AD9393 is interfacing with lower voltage logic, VDD can be connected to a
lower supply voltage (as low as 1.8 V) for compatibility.
PLL Power Supply (1.8 V). The most sensitive portion of the AD9393 is the
clock generation circuitry. These pins provide power to the clock PLL and help
the user design for optimal performance. The user should provide quiet,
noise-free power to these pins.
Digital Logic Power Supply (1.8 V). These pins supply power to the digital
logic.
Ground. The ground return for all circuitry on chip. It is recommended that the
AD9393 be assembled on a single solid ground plane, with careful attention
to ground current paths.
3.3 V
1.8 V to 3.3
V
1.8 V
1.8 V
0V
Serial Port Data I/O for Programming the AD9393 Registers. The I2C address is
Address 0x98.
Serial Port Data Clock for Programming the AD9393 Registers.
3.3 V CMOS
3.3 V CMOS
HDCP Slave Serial Port Data Clock for HDCP Communications to Transmitter.
HDCP Slave Serial Port Data I/O for HDCP Communications to Transmitter. The
I2C address is Address 0x74 or Address 0x76.
Master Serial Port I/O to EEPROM with HDCP Keys—I2C Address is 0xA0.
Master Serial Port Data Clock to EEPROM with HDCP Keys.
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
S/PDIF Digital Audio Output.
VDD
I2S Audio (Channel 1, Channel 2). Channel 0 and Channel 1 Audio Output.
VDD
I2S Audio (Channel 3, Channel 4). Channel 2 and Channel 3 Audio Output.
VDD
I2S Audio (Channel 5, Channel 6). Channel 4 and Channel 5 Audio Output.
VDD
I2S Audio (Channel 7, Channel 8). Channel 6 and Channel 7 Audio Output.
VDD
Audio Master Clock Output for S/PDIF Data.
VDD
Audio Serial Clock Output for I2S Data.
VDD
Data Output Clock for Left and Right Audio Channels.
VDD
Data Enable for Active Data Pixels.
3.3 V CMOS
Sets Internal Termination Resistance. Place a 500 Ω (1% tolerance) resistor from 500 Ω
this pin to ground. This sets the internal termination of TMDS lines to 50 Ω.
1 The supplies should be sequenced such that VD and VDD are never less than 300 mV below DVDD. At no time should DVDD be more than 300 mV greater than VD or VDD.
Rev. 0 | Page 7 of 40

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