AD9444 查看數據表（PDF） - Analog Devices
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AD9444 Datasheet PDF : 40 Pages
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AD9444
DC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed
reference (1.0 V mode), AIN = −0.5 dBFS, DCS on, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error1
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error
Gain Error
VOLTAGE REFERENCE
Output Voltage1
Load Regulation @ 1.0 mA
Reference Input Current (External 1.0 V Reference)
INPUT REFERRED NOISE
ANALOG INPUT
Input Span
Input Common-Mode Voltage
Input Resistance3
Input Capacitance3
POWER SUPPLIES
Supply Voltage
AVDD1
AVDD2
DRVDD—LVDS Outputs
DRVDD—CMOS Outputs
Supply Current
AVDD1
AVDD22
IDRVDD2—LVDS Outputs
IDRVDD2—CMOS Outputs
PSRR
Offset
Gain
POWER CONSUMPTION
DC Input—LVDS Outputs
DC Input—CMOS Outputs
Sine Wave Input2—LVDS Outputs
Sine Wave Input2—CMOS Outputs
Temp
Full
Test Level
VI
Full
VI
Full
VI
Full
VI
Full
VI
25°C I
Full
VI
Full
V
Full
V
Full
VI
Full
V
Full
VI
25°C V
Full
V
Full
V
Full
V
Full
V
AD9444BSVZ-80
Min Typ
Max Unit
14
Bits
Guaranteed
6
±0.3
−3.0 ±0.4
−0.8 ±0.4
−1.3 ±0.6
−1.7
6
mV
+3.0 % FSR
+0.8 LSB
+1.3 LSB
+1.7 LSB
12
0.002
µV/°C
%FS/°C
0.87 1.0
±2
80
1.0
1.13 V
mV
125 µA
LSB rms
2
V p-p
3.5
V
1
kΩ
2.5
pF
Full
IV
Full
IV
Full
IV
Full
IV
Full
VI
Full
VI
Full
VI
Full
V
Full
V
Full
V
Full
VI
Full
V
Full
VI
Full
V
3.14 3.3
4.75 5.0
3.0
3.0 3.3
217
71
55
12
1
0.2
1.21
1.07
1.25
1.11
3.46 V
5.25 V
3.6 V
3.6 V
240 mA
80
mA
62
mA
mA
mV/V
%/V
1.4 W
W
W
W
1 The internal voltage reference is trimmed at final test to minimize the gain error of the AD9444.
2 Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
3 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input
structure.
Rev. 0 | Page 3 of 40
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