AD9445 查看數據表（PDF） - Analog Devices

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AD9445

14-Bit, 105/125 MSPS, IF Sampling ADC

Analog Devices 

TIMING DIAGRAMS

N–1

N

AIN

N+1

CLK+

CLK–

DATA OUT

DCO+

tCLKL

tCLKH

1/fS

tPD

N – 13

N – 12

13 CLOCK CYCLES

N

N+1

DCO–

VIN

CLK–

tCPD

N

N–1

tCLKL

tCLKH

N+1

Figure 2. LVDS Mode Timing Diagram

N+2

CLK+

tPD

13 CLOCK CYCLES

DX

N – 13

N – 12

N–1

N

DCO+

DCO–

Figure 3. CMOS Timing Diagram

AD9445

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