AD9524 查看數據表（PDF） - Analog Devices
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AD9524 Datasheet PDF : 56 Pages
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AD9524
Data Sheet
SPECIFICATIONS
fVCXO = 122.88 MHz single-ended, REFA and REFB on differential at 30.72 MHz, fVCO = 3932.16 MHz, doubler is off, channel control
low power mode off, divider phase =1, unless otherwise noted. Typical is given for VDD = 3.3 V ± 5%, and TA = 25°C, unless otherwise
noted. Minimum and maximum values are given over the full VDD and TA (−40°C to +85°C) variation, as listed in Table 1.
CONDITIONS
Table 1.
Parameter
Min Typ Max
SUPPLY VOLTAGE
VDD3_PLL1, Supply Voltage for PLL1
3.3
VDD3_PLL2, Supply Voltage for PLL2
3.3
VDD3_REF, Supply Voltage Clock Output Drivers Reference
3.3
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
3.3
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers
1.8
TEMPERATURE
Ambient Temperature Range, TA
−40 +25 +85
Junction Temperature, TJ
115
Unit Test Conditions/Comments
V
3.3 V ± 5%
V
3.3 V ± 5%
V
3.3 V ± 5%
V
3.3 V ± 5%
V
1.8 V ± 5%
°C
°C
1 x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 41 and Pin 40,
respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 38 and Pin 37, respectively).
SUPPLY CURRENT
Table 2.
Parameter
SUPPLIES OTHER THAN CLOCK OUTPUT DRIVERS
VDD3_PLL1, Supply Voltage for PLL1
VDD3_PLL2, Supply Voltage for PLL2
VDD3_REF, Supply Voltage Clock Output Drivers
Reference
LVPECL Mode
LVDS Mode
HSTL Mode
CMOS Mode
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers2
CLOCK OUTPUT DRIVERS—LOWER POWER MODE OFF
LVDS Mode, 7 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
LVDS Mode, 3.5 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
LVPECL Compatible Mode
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
HSTL Mode, 8 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
CMOS Mode (Single-Ended)
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
Min Typ Max
37 43
67 77.7
5
6
4
4.8
3
3.6
3
3.6
3.5 4.2
11.5 13.2
40 45
6.5 7.5
23 26.3
13 14.4
41 46.5
14 16.3
2
2.4
Unit Test Conditions/Comments
mA Decreases by 9 mA typical if REFB is turned
off
mA
mA Only one output driver turned on; for each
additional output that is turned on, the current
increments by 1.2 mA maximum
mA Only one output driver turned on; for each
additional output that is turned on, the current
increments by 1.2 mA maximum
mA Values are independent of the number of
outputs turned on
mA Values are independent of the number of
outputs turned on
mA Current for each divider: f = 245.76 MHz
Channel x control register, Bit 4 = 0
mA f = 122.88 MHz
mA f = 983.04 MHz
mA f = 122.88 MHz
mA f = 983.04 MHz
mA f = 122.88 MHz
mA f = 983.04 MHz
mA f = 122.88 MHz
mA f = 15.36 MHz, 10 pF load
Rev. D | Page 4 of 56
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