AD9525(Rev0) 查看數據表（PDF） - Analog Devices
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AD9525 Datasheet PDF : 48 Pages
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AD9525
Data Sheet
PLL DIGITAL LOCK DETECT
Table 8.
Parameter
Min
PLL DIGITAL LOCK DETECT WINDOW1
Lock Threshold (Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Unlock Threshold (Hysteresis)1
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Typ Max Unit Test Conditions/Comments
Signal available at the STATUS and REF_MON pins when
selected by appropriate register settings; lock detect window
settings can be varied by changing the CPRSET resistor
Selected by Reg. 0x010[1:0] and Reg. 0x019[1], which is the
threshold for transitioning from unlock to lock
4
ns
Reg. 0x010[1:0] = 00b, 01b,11b; Reg. 0x019[1] = 1b
7
ns Reg. 0x010[1:0] = 00b, 01b, 11b; Reg. 0x019[1] = 0b
3.5
ns
Reg. 0x010[1:0] = 10b; Reg. 0x019[1] = 0b
Selected by Reg. 0x017[1:0] and Reg. 0x019[1], which is the
threshold for transitioning from unlock to lock
8.3
ns
Reg. 0x010[1:0] = 00b, 01b, 11b; Reg. 0x019[1] = 1b
16.9
ns Reg. 0x010[1:0] = 00b, 01b, 11b; Reg. 0x019[1] = 0b
11
ns
Reg. 0x010[1:0] = 10b; Reg. 0x019[1] = 0b
1 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
CLOCK OUTPUTS
Table 9.
Parameter
LVPECL CLOCK OUTPUTS
Output Frequency, Maximum
Rise Time/Fall Time (20% to 80%)
Duty Cycle
M=1
M = 2, 4, 6
M = 3, 5
Output Differential Voltage,
Magnitude
Common-Mode Output Voltage
Min
Typ
Max
Unit Test Conditions/Comments
3.6
47
45
47
45
32
750
VDD3 –
1.42
105
50
50
49
49
32
830
VDD3 –
1.37
162
53
55
51
55
33
984
VDD3 –
1.32
GHz
ps
Input duty cycle = 50/50
% FOUT = 2800 MHz
% FOUT < 3000 MHz
% FOUT = 1400 MHz
% FOUT < 1500 MHz
% FOUT = 933.33 MHz
mV Voltage across pins, output driver static;
Termination = 50 Ω to VDD3 − 2 V
V
Output driver static; VDD3 (Pin 3, Pin 36, Pin 41, Pin 46);
Termination = 50 Ω to VDD3 − 2 V
Rev. 0 | Page 6 of 48
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