AD9557BCPZ-REEL7(RevA) 查看數據表（PDF） - Analog Devices

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AD9557BCPZ-REEL7
(Rev.:RevA)

Dual Input Multiservice Line Card Adaptive Clock Translator

Analog Devices 

AD9557

Parameter

Min

OUTPUT TIMING SKEW

Between OUT0 and OUT1

Additional Delay on One Driver by

Changing Its Logic Type

HSTL to LVDS

−5

HSTL to 1.8 V CMOS

−5

OUT1 HSTL to OUT0 3.3 V CMOS,

Strong Mode

1 The listed values are for the slower edge (rise or fall).

Typ Max

10

70

+1

+5

0

+5

3.53 3.59

TIME DURATION OF DIGITAL FUNCTIONS

Table 11.

Parameter

Min

TIME DURATION OF DIGITAL FUNCTIONS

EEPROM-to-Register Download Time

Typ Max

13

20

Register-to-EEPROM Upload Time

Minimum Power-Down Exit Time

138 145

1

Data Sheet

Unit Test Conditions/Comments

10 pF load

ps HSTL mode on both drivers; rising edge only;

any divide value

ps Positive value indicates that the LVDS edge is

delayed relative to HSTL

ps Positive value indicates that the CMOS edge is

delayed relative to HSTL

ns The CMOS edge is delayed relative to HSTL

Unit Test Conditions/Comments

ms Using default EEPROM storage sequence

(see Register 0x0E10 to Register 0x0E3F)

ms Using default EEPROM storage sequence

(see Register 0x0E10 to Register 0x0E3F

ms Time from power-down exit to system clock lock detect

Rev. A | Page 10 of 92

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