AD9557/PCBZ(RevA) 查看數據表（PDF） - Analog Devices

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AD9557/PCBZ
(Rev.:RevA)

Dual Input Multiservice Line Card Adaptive Clock Translator

Analog Devices 

Data Sheet

AD9557

DIGITAL PLL

Table 12.

Parameter

Min

DIGITAL PLL

Phase-Frequency Detector (PFD)

2

Input Frequency Range

Loop Bandwidth

0.1

Phase Margin

30

Closed-Loop Peaking

<0.1

Reference Input (R) Division Factor 1

Integer Feedback (N1) Division Factor 180

Fractional Feedback Divide Ratio

0

DIGITAL PLL LOCK DETECTION

Table 13.

Parameter

PHASE LOCK DETECTOR

Threshold Programming Range

Threshold Resolution

FREQUENCY LOCK DETECTOR

Threshold Programming Range

Threshold Resolution

Min

0.001

0.001

HOLDOVER SPECIFICATIONS

Table 14.

Parameter

Min

HOLDOVER SPECIFICATIONS

Initial Frequency Accuracy

Typ

Typ

1

1

Typ

<0.01

Max

100

2000

89

220

217

0.999

Unit

Test Conditions/Comments

kHz

Hz

Degrees

dB

Programmable design parameter

Programmable design parameter

Programmable design parameter; part can be

programmed for <0.1 dB peaking in accordance with

Telcordia GR-253 jitter transfer

1, 2, …, 1,048,576

180, 181, …, 131,072

Maximum value: 16,777,215/16,777,216

Max Unit

65.5

ns

ps

16,700 ns

ps

Test Conditions/Comments

Reference-to-feedback period difference

Max

Unit

ppm

Test Conditions/Comments

Excludes frequency drift of SYSCLK source; excludes

frequency drift of input reference prior to entering

holdover; compliant with GR-1244 Stratum 3

Rev. A | Page 11 of 92

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