AD9557BCPZ-REEL7(RevA) 查看數據表（PDF） - Analog Devices

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AD9557BCPZ-REEL7
(Rev.:RevA)

Dual Input Multiservice Line Card Adaptive Clock Translator

Analog Devices 

AD9557

Data Sheet

REFERENCE MONITORS

Table 8.

Parameter

REFERENCE MONITORS

Reference Monitor

Loss of Reference Detection Time

Frequency Out-of Range Limits

Validation Timer

Min

Typ Max

Unit

Test Conditions/Comments

<2

0.001

1.1

105

65.535

DPLL PFD

period

Δf/fREF

(ppm)

sec

Nominal phase detector period = R/fREF 1

Programmable (lower bound is subject to quality

of the system clock (SYSCLK)); SYSCLK accuracy

must be better than the lower bound

Programmable in 1 ms increments

1 fREF is the frequency of the active reference; R is the frequency division factor determined by the R divider.

REFERENCE SWITCHOVER SPECIFICATIONS

Table 9.

Parameter

Min

REFERENCE SWITCHOVER SPECIFICATIONS

Maximum Output Phase Perturbation

(Phase Build-Out Switchover)

50 Hz DPLL Loop Bandwidth

Peak

Steady State

2 kHz DPLL Loop Bandwidth

Peak

Steady State

Time Required to Switch to a New Reference

Phase Build-Out Switchover

Typ Max Unit

0

±100 ps

0

±100 ps

0

±250 ps

0

±100 ps

Test Conditions/Comments

Assumes a jitter-free reference; satisfies

Telcordia GR-1244-CORE requirements; select

high PM base loop filter bit (Register 0x070E, Bit 0)

is set to 1 for all active references

Valid for automatic and manual reference

switching

Valid for automatic and manual reference

switching

1.1

DPLL PFD Calculated using the nominal phase detector

period

period (NPDP = R/fREF); the total time required is

equal to the time plus the reference validation

time and the time required to lock to the new

reference

Rev. A | Page 8 of 92

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