AD9557BCPZ-REEL7 查看數據表（PDF） - Analog Devices
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AD9557BCPZ-REEL7 Datasheet PDF : 95 Pages
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Data Sheet
AD9557
IRQ Mask (Register 0x020A to Register 0x020F)...................71
DPLL Configuration (Register 0x0300 to Register 0x032E).......72
Output PLL Configuration (Register 0x0400 to
Register 0x0408)..........................................................................75
Output Clock Distribution (Register 0x0500 to
Register 0x0515)..........................................................................77
Reference Inputs (Register 0x0600 to Register 0x0602) ........79
DPLL Profile Registers (Register 0x0700 to
Register 0x0766)..........................................................................79
Operational Controls (Register 0x0A00 to
Register 0x0A0D)........................................................................82
Quick In/Out Frequency Soft Pin Configuration
(Register 0x0C00 to Register 0x0C08) .....................................85
Status Readback (Register 0x0D00 to Register 0x0D14) .......86
EEPROM Control (Register 0x0E00 to Register 0x0E3C)....... 89
EEPROM Storage Sequence (Register 0x0E10 to
Register 0x0E3C).........................................................................89
Outline Dimensions........................................................................95
Ordering Guide ...........................................................................95
REVISION HISTORY
9/2016—Rev. B to Rev. C
Changes to Chip Power Monitor and Startup, Device Register
Changes to Features Section, Applications Section, and General
Programming Using a Register Setup File, and Registers That
Description Section...........................................................................1
Differ from the Defaults for Optimal Performance Sections....25
Change to Input Frequency Range Parameter, Table 6 ................7
Changes to Initialize and Calibrate the Output PLL (APLL)
Change to Common-Mode Input Voltage Parameter, Table 7.......8
Section ..............................................................................................26
Changes to Table 20 ........................................................................18
Changes to Program the Reference Profiles Section; Changed
Changes to Chip Power Monitor and Startup Section and Device
Lock the Digital PLL Section Name to Generate the Reference
Register Programming Using a Register Setup File Section......26
Acquisition; Changes to Generate the Reference Acquisition
Added Figure 35 to Figure 37; Renumbered Sequentially .........26
Section ..............................................................................................27
Changes to Figure 38 and Overview Section...............................30
Changes to Figure 35; Changed 225 MHz to 200 MHz and
Changes to System Clock Details Section....................................35
3.45 GHz to 3.35 GHz in Overview Section................................28
Added RF Dividers (RF Divider 2 and RF Divider 1) Section.....38
Changed 180 MHz to 175 MHz in DPLL Overview Section ....30
Changes to IRQ Pin Section ..........................................................40
Changed DPLL Output Frequency to DCO Frequency
Changes to Table 21 ........................................................................42
Throughout; Changes to Programmable Digital Loop Filter
Changes to Manual EEPROM Download Section, Automatic
Section ..............................................................................................31
EEPROM Download Section, and Table 22 ................................43
Changes to System Clock Inputs Section.....................................33
Changes to EEPROM Conditional Processing Section..............44
Changed VCO2 Lower Frequency to 3.35 GHz in Figure 39;
Changes to Programming the EEPROM to Configure an M Pin
Changes to Output PLL (APLL) Section .....................................35
to Control Synchronization of Clock Distribution Section.......46
Changed 1024 to 1023 in Clock Dividers Section;
Changes to Power Supply Partitions Section and Use of Ferrite
Changes to Divider Synchronization Section..............................36
Beads on 1.8 V Supplies Section....................................................56
Changes to the Multifunction Pins (M0 to M3) Section ...........37
Changes to Table 35 ........................................................................59
Added the Programming the EEPROM to Configure an M Pin to
Added Note 1, Table 44 ..................................................................69
Control Synchronization of the Clock Distribution Section.....42
Changes to Table 47 ........................................................................70
Changes to the Power Supply Partitions Section ........................53
Changes to Table 64 ........................................................................75
Changed 89.5° to 88.5° in DPLL Phase Margin Section ............54
Changes to Table 65 ........................................................................76
Changes to Register 0x000A, Table 35 .........................................56
Changes to Table 83 and Table 84 .................................................81
Changes to Register 0x0304, Table 35 ..........................................57
Changes to Status Readback (Register 0x0D00 to
Change to Default Value in Register 0x0400 and Register 0x0403;
Register 0x0D14) Section and Table 99........................................86
Changes to Register 0x0405, Table 35 ..........................................58
Added Note 1, Table 107 ................................................................88
Change to Bit 0, Register 0x070E, Table 35 .................................59
Changes to Table 110 ......................................................................89
Change to Bit 6, Register 0x0D01, Table 35.................................63
Added Address 0x0E3D to Address 0xE45, Table 35 .................64
5/2013—Rev. A to Rev. B
Changes to Description, Register 0x0005, Table 38;
Change to Register 0x0101, Bit 4; Table 35..................................56
Added Table 40, Renumbered Sequentially; Changes to
Changes to Bit 4; Table 43 ..............................................................66
Descriptions, Register 0x000C and Register 0x000D, Table 41...65
Changes to Summary Text, Register 0x0200 to
3/2012—Rev. 0 to Rev. A
Register 0x0209, Table 46 and Table 47........................................67
Change to Output Frequency Range Parameter, Table 6 .............6
Changes to Register 0x0304, Table 54; Change to Bits[7:6],
Changes to Test Conditions/Comments Column, Table 9 ..........8
Table 55.............................................................................................69
Changed Name of Pin 21 in Figure 2............................................17
Changes to Table Title, Table 63; Changes to Description,
Changes to Table 20 ........................................................................18
Register 0x0400 and Register 0x0403, Table 64 ..........................72
Rev. C | Page 3 of 95
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