AD9557BCPZ-REEL7 查看數據表（PDF） - Analog Devices

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AD9557BCPZ-REEL7

Dual Input Multiservice Line Card Adaptive Clock Translator

Analog Devices 

Data Sheet

LOGIC OUTPUTS (M3 TO M0, IRQ)

Table 5.

Parameter

LOGIC OUTPUTS (M3 to M0, IRQ)

Output High Voltage (VOH)

Output Low Voltage (VOL)

IRQ Leakage Current

Active Low Output Mode

Active High Output Mode

Min

Typ

DVDD3 − 0.4

SYSTEM CLOCK INPUTS (XOA, XOB)

Table 6.

Parameter

SYSTEM CLOCK MULTIPLIER

Output Frequency Range

Min

Typ

750

Phase Frequency Detector (PFD) Rate

Frequency Multiplication Range

2

SYSTEM CLOCK REFERENCE INPUT PATH

Input Frequency Range

10

Minimum Input Slew Rate

20

Common-Mode Voltage

1.05

1.16

Differential Input Voltage Sensitivity

250

Max

0.4

−200

100

Max

805

150

255

600

1.25

System Clock Input Doubler Duty Cycle

System Clock Input = 50 MHz

45

System Clock Input = 20 MHz

46

System Clock Input = 16 MHz to 20 MHz 47

Input Capacitance

Input Resistance

CRYSTAL RESONATOR PATH

Crystal Resonator Frequency Range

10

Maximum Crystal Motional Resistance

50

55

50

54

50

53

3

4.2

50

100

AD9557

Unit

V

V

µA

µA

Test Conditions/Comments

IOH = 1 mA

IOL = 1 mA

Open-drain mode

VOH = 3.3 V

VOL = 0 V

Unit Test Conditions/Comments

MHz The VCO range may place limitations on

nonstandard system clock input frequencies

MHz

Assumes valid system clock and PFD rates

MHz

V/µs

V

mV p-p

%

%

%

pF

kΩ

Minimum limit imposed for jitter

performance

Internally generated

Minimum voltage across pins required to

ensure switching between logic states;

the instantaneous voltage on either pin

must not exceed the supply rails;

can accommodate single-ended input by

ac grounding of complementary input;

1 V p-p recommended for optimal jitter

performance

This is the amount of duty cycle variation

that can be tolerated on the system clock

input to use the doubler

Single-ended, each pin

MHz Fundamental mode, AT cut crystal

Ω

Rev. C | Page 7 of 95

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