AD9557BCPZ-REEL7 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

AD9557BCPZ-REEL7

Dual Input Multiservice Line Card Adaptive Clock Translator

Analog Devices 

Data Sheet

AD9557

REFERENCE MONITORS

Table 8.

Parameter

REFERENCE MONITORS

Reference Monitor

Loss of Reference Detection Time

Frequency Out-of Range Limits

Validation Timer

Min

Typ Max

Unit

Test Conditions/Comments

<2

0.001

1.1

105

65.535

DPLL PFD

period

Δf/fREF

(ppm)

sec

Nominal phase detector period = R/fREF1

Programmable (lower bound is subject to quality

of the system clock (SYSCLK)); SYSCLK accuracy

must be better than the lower bound

Programmable in 1 ms increments

1 fREF is the frequency of the active reference; R is the frequency division factor determined by the R divider.

REFERENCE SWITCHOVER SPECIFICATIONS

Table 9.

Parameter

Min

Typ

REFERENCE SWITCHOVER SPECIFICATIONS

Maximum Output Phase Perturbation

(Phase Build-Out Switchover)

50 Hz DPLL Loop Bandwidth

Peak

0

Steady State

0

2 kHz DPLL Loop Bandwidth

Peak

0

Steady State

0

Time Required to Switch to a New Reference

Phase Build-Out Switchover

Max

±100

±100

±250

±100

1.1

Unit

Test Conditions/Comments

Assumes a jitter-free reference; satisfies

Telcordia GR-1244-CORE requirements; select

high PM base loop filter bit (Register 0x070E, Bit 0)

is set to 1 for all active references

Valid for automatic and manual reference

switching

ps

ps

Valid for automatic and manual reference

switching

ps

ps

DPLL PFD

period

Calculated using the nominal phase detector

period (NPDP = R/fREF); the total time required is

equal to the time plus the reference validation

time and the time required to lock to the new

reference

Rev. C | Page 9 of 95

Share Link: