AD9573 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

AD9573

PCI-Express Clock Generator IC, PLL Core, Dividers, Two Outputs

Analog Devices 

AD9573

evaluation board shows a good example (see the Ordering

Guide for information about the evaluation board).

LVDS CLOCK DISTRIBUTION

Low voltage differential signaling (LVDS) is the differential

output for the AD9573. LVDS uses a current mode output stage

with a factory programmed current level. The normal value

(default) for this current is 6.5 mA, which yields a 650 mV

output swing across a 100 Ω resistor.

The typical termination circuit for the LVDS outputs is shown

in Figure 11.

50Ω

LVDS

100Ω

LVDS

50Ω

Figure 11. LVDS Output Termination

An alternative method of terminating the output to preserve output

swing but also minimize reflections is shown in Figure 12.

50Ω

LVDS

200Ω

200Ω

LVDS

50Ω

Figure 12. Alternative LVDS Output Termination

CMOS CLOCK DISTRIBUTION

The AD9573 provides a 33.33 MHz clock output, which is a

dedicated CMOS level. Whenever single-ended CMOS clocking

is used, some of the following general guidelines should be

followed.

Point-to-point nets should be designed such that a driver has

one receiver only on the net, if possible. This allows for simple

termination schemes and minimizes ringing due to possible

mismatched impedances on the net. Series termination at the

source is generally required to provide transmission line

matching and/or to reduce current transients at the driver. The

value of the resistor is dependent on the board design and

timing requirements (typically 10 Ω to 100 Ω is used). CMOS

outputs are limited in terms of the capacitive load or trace

length that they can drive. Typically, trace lengths less than

6 inches are recommended to preserve signal rise/fall times

and preserve signal integrity.

CMOS

60.4Ω

10Ω 1.0 INCH

MICROSTRIP

5pF

GND

Figure 13. Series Termination of CMOS Output

Termination at the far end of the PCB trace is a second option.

The CMOS output of the AD9573 does not supply enough

current to provide a full voltage swing with a low impedance

resistive, far end termination, as shown in Figure 14. The far

end termination network should match the PCB trace

impedance and provide the desired switching point.

The reduced signal swing may still meet receiver input require-

ments in some applications. This can be useful when driving

long trace lengths on less critical nets.

VPULLUP = 3.3V

10Ω

50Ω

CMOS

100Ω

100Ω

3pF

Figure 14. CMOS Output with Far-End Termination

POWER AND GROUNDING CONSIDERATIONS AND

POWER SUPPLY REJECTION

Many applications seek high speed and performance under

less than ideal operating conditions. In these application

circuits, the implementation and construction of the PCB is as

important as the circuit design. Proper RF techniques must be

used for device selection, placement, and routing, as well as for

power supply decoupling and grounding to ensure optimum

performance.

Rev. 0 | Page 10 of 12

Share Link: