AD9575(Rev0) 查看數據表（PDF） - Analog Devices

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产品描述 (功能)

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AD9575
(Rev.:Rev0)

Network Clock Generator, Two Outputs

Analog Devices 

AD9575

–110

–115

–120

–125

–130

–135

–140

–145

–150

–155

–160

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 11. Phase Noise at LVPECL, 312.5 MHz Clock Output

140

130

LVDS POWER

120

110

LVPECL POWER

100

90

80

1

2

3

4

5

6

7

8

MODE

Figure 12. Typical Power Dissipation vs. Mode

M2

M2 100mV 1ns

M3 100mV 1ns

Figure 14. 312.5 MHz LVPECL Output

M2

M2 100mV 10ns

M3 100mV 10ns

Figure 15. 62.5 MHz LVCMOS Output

M2

M2 50mV 2ns

M3 50mV 2ns

Figure 13. 156.25 MHz LVDS Output

Rev. 0 | Page 10 of 16

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