AD9628(Rev0) 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
AD9628 Datasheet PDF : 44 Pages
| |||
AD9628
VIN
CLK+
CLK–
DCOA/DCOB
CH A DATA
CH B DATA
N–1
tCH
tA
N
N+1
tCLK
N+2
N+3
N+4
N+5
tDCO
tSKEW
CH A CH B CH A CH B CH A CH B CH A CH B
N – 16 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 N – 9
tPD
CH B CH A CH B CH A CH B CH A CH B CH A
N – 16 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 N – 9
CH A
N–8
CH B
N–8
Figure 3. CMOS Interleaved Output Mode Data Output Timing
VIN
CLK+
CLK–
DCO–
DCO+
PARALLEL
INTERLEAVED
MODE
D0+ (LSB)
D0– (LSB)
D11+ (MSB)
D11– (MSB)
CHANNEL
MULTIPLEXED
MODE
CHANNEL A
D1+/D0+ (LSB)
D1–/D0– (LSB)
D11+/D10+ (MSB)
D11–/D10– (MSB)
CHANNEL
MULTIPLEXED
MODE
CHANNEL B
D1+/D0+ (LSB)
D1–/D0– (LSB)
D11+/D10+ (MSB)
D11–/D10– (MSB)
N–1
tCH
tA
N
N+1
tCLK
N+2
N+3
N+4
N+5
tDCO
tPD
tSKEW
CH A CH B CH A CH B CH A CH B CH A CH B CH A
N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12
CH A CH B CH A CH B CH A CH B CH A CH B CH A
N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12
CH A0 CH A1 CH A0 CH A1 CH A0 CH A1 CH A0 CH A1 CH A0
N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12
CH A10 CH A11 CH A10 CH A11 CH A10 CH A11 CH A10 CH A11 CH A10
N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12
CH B0 CH B1 CH B0 CH B1 CH B0 CH B1 CH B0 CH B1 CH B0
N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12
CH B10 CH B11 CH B10 CH B11 CH B10 CH B11 CH B10 CH B11 CH B10
N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12
Figure 4. LVDS Modes for Data Output Timing
Rev. 0 | Page 10 of 44
Share Link: 