AD9640 查看數據表（PDF） - Analog Devices
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AD9640 Datasheet PDF : 52 Pages
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AD9640
Parameter
CMOS Mode Pipeline Delay (Latency)
LVDS Mode Pipeline Delay (Latency)
Channel A/Channel B
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time3
OUT-OF-RANGE RECOVERY TIME
Temp
Full
Full
Full
Full
Full
AD9640ABCPZ-80
AD9640BCPZ-80
Min
Typ
Max
12
12/12.5
1.0
0.1
350
2
1 Conversion rate is the clock rate after the divider.
2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
3 Wake-up time is dependent on the value of the decoupling capacitors.
AD9640ABCPZ-105/
AD9640BCPZ-105
Min
Typ
Max
12
12/12.5
1.0
0.1
350
2
Unit
Cycles
Cycles
ns
ps rms
μs
Cycles
SWITCHING SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND
AD9640BCPZ-150
AVDD = 1.8 V, DVDD = 1.8V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS
enabled, unless otherwise noted.
Table 7.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate
DCS Enabled1
DCS Disabled1
CLK Period—Divide by 1 Mode (tCLK)
CLK Pulse Width High
Divide by 1 Mode, DCS Enabled
Divide by 1 Mode, DCS Disabled
Divide by 2 Mode, DCS Enabled
Divide by 3 Through 8, DCS Enabled
DATA OUTPUT PARAMETERS (DATA, FD)
CMOS Mode—DRVDD = 3.3 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
CMOS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
LVDS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
CMOS Mode Pipeline Delay (Latency)
LVDS Mode Pipeline Delay (Latency)
Channel A/Channel B
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time3
OUT-OF-RANGE RECOVERY TIME
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9640ABCPZ-125/
AD9640BCPZ-125
Min
Typ
Max
625
20
125
10
125
8
2.4
4
5.6
3.6
4
4.4
1.6
0.8
2.2
4.5
6.4
3.8
5.0
6.8
4.5
3.5
2.4
5.2
6.9
4.0
5.6
7.3
3.0
3.8
4.5
5.0
6.2
7.4
12
12/12.5
1.0
0.1
350
3
AD9640ABCPZ-150/
AD9640BCPZ-150
Min
Typ
Max
625
20
150
10
150
6.66
2.0
3.33
4.66
3.0
3.33
3.66
1.6
0.8
2.2
4.5
6.4
3.8
5.0
6.8
3.83
2.83
2.4
5.2
6.9
4.0
5.6
7.3
3.0
3.8
4.5
4.8
5.9
7.3
12
12/12.5
1.0
0.1
350
3
Unit
MHz
MSPS
MSPS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
Cycles
ns
ps rms
μs
Cycles
1 Conversion rate is the clock rate after the divider.
2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
3 Wake-up time is dependent on the value of the decoupling capacitors.
Rev. B | Page 11 of 52
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