AD9717(RevB) 查看數據表（PDF） - Analog Devices
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AD9717
(Rev.:RevB)
(Rev.:RevB)
Analog Devices
AD9717 Datasheet PDF : 80 Pages
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AD9714/AD9715/AD9716/AD9717
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Data Sheet
DB5 1
DB4 2
DB3 3
DB2 4
DVDDIO 5
DVSS 6
DVDD 7
DB1 8
DB0 (LSB) 9
NC 10
PIN 1
INDICATOR
AD9714
TOP VIEW
(Not to Scale)
30 RLIN
29 IOUTN
28 IOUTP
27 RLIP
26 AVDD
25 AVSS
24 RLQP
23 QOUTP
22 QOUTN
21 RLQN
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PAD IS CONNECTED TO AVSS AND
SHOULD BE SOLDERED TO THE GROUND PLANE.
EXPOSED METAL AT PACKAGE CORNERS IS
CONNECTED TO THIS PAD.
Figure 2. AD9714 Pin Configuration
Table 7. AD9714 Pin Function Descriptions
Pin No. Mnemonic
Description
1 to 4
DB[5:2]
Digital Inputs.
5
DVDDIO
Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal).
6
DVSS
Digital Common.
7
DVDD
Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a
1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
8
DB1
Digital Inputs.
9
DB0 (LSB)
Digital Input (LSB).
10 to 15 NC
No Connect. These pins are not connected to the chip.
16
DCLKIO
Data Input/Output Clock. Clock used to qualify input data.
17
CVDD
Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
18
CLKIN
LVCMOS Sampling Clock Input.
19
CVSS
Sampling Clock Supply Voltage Common.
20
CMLQ
Q DAC Output Common-Mode Level. When the internal on chip (QRCML) is enabled, this pin is connected to
the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip
(QRCML) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a
resistor (see the Using the Internal Termination Resistors section). The recommended value for this external
resistor is 0 Ω.
21
RLQN
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.
22
QOUTN
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
23
QOUTP
Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
24
RLQP
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
25
AVSS
Analog Common.
26
AVDD
Analog Supply Voltage (1.8 V to 3.3 V).
27
RLIP
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
28
IOUTP
I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
29
IOUTN
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
30
RLIN
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
Rev. B | Page 10 of 80
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