AD9717(RevB) 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

AD9717
(Rev.:RevB)

Dual, Low Power, 8-/10-/12-/14-Bit TxDAC Digital-to-Analog Converters

Analog Devices 

Data Sheet

AD9714/AD9715/AD9716/AD9717

Pin No.

31

32

33

34

35

36

37

38

39

40

41 (EPAD)

Mnemonic

CMLI

FSADJQ/AUXQ

FSADJI/AUXI

REFIO

RESET/PINMD

SCLK/CLKMD

SDIO/FORMAT

CS/PWRDN

DB7 (MSB)

DB6

Exposed Pad

(EPAD)

Description

I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the

on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip (IRCML) is

disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor

(see the Using the Internal Termination Resistors section). The recommended value for this external resistor

is 0 Ω.

Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full-

scale current output adjust for Q DAC and must be connected to AVSS through a resistor (see the Theory of

Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.

Auxiliary Q DAC Output (AUXQ). When the internal on chip (QRSET) is enabled, this pin is the auxiliary Q DAC

output.

Full-Scale Current Output Adjust (FSADJI). When the internal on chip (IRSET) is disabled, this pin is full-scale

current output adjust for I DAC and must be connected to AVSS through a resistor (see the Theory of

Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.

Auxiliary I DAC Output (AUXI). When the internal on chip (IRSET) is enabled, this pin is the auxiliary I DAC

output.

Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V

reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).

This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.

Pulse RESET high to reset the SPI registers to their default values.

A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).

Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.

Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When

DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer (see the

Retimer section).

Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for serial port.

Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-

down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the two

complement input data format.

Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select. In pin mode, a logic

high (pull-up to DVDDIO) powers down the device, except for the SPI port.

Power-Down (PWRDN). In pin mode, PWRDN powers down the device except for the SPI port.

Digital Input (MSB).

Digital Input.

The exposed pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at the

package corners is connected to this pad.

Rev. B | Page 11 of 80

Share Link: