AD9765-EB 查看數據表（PDF） - Analog Devices

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AD9765-EB

12-Bit, 125 MSPS Dual TxDAC+® D/A Converter

Analog Devices 

AD9765–SPECIFICATIONS

DC SPECIFICATIONS (TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted.)

Parameter

Min

Typ

Max

RESOLUTION

DC ACCURACY1

Integral Linearity Error (INL)

TA = +25°C

TMIN to TMAX

Differential Nonlinearity (DNL)

TA = +25°C

TMIN to TMAX

ANALOG OUTPUT

Offset Error

Gain Error (Without Internal Reference)

Gain Error (With Internal Reference)

Gain Match

Full-Scale Output Current2

Output Compliance Range

Output Resistance

Output Capacitance

12

–1.5

–2.0

–0.75

–1.0

–0.02

–2

–5

–1.6

–0.14

2.0

–1.0

± 0.4

± 0.3

± 0.25

±1

0.1

100

5

+1.5

+2.0

+0.75

+1.0

+0.02

+2

+5

+1.6

+0.14

20.0

+1.25

REFERENCE OUTPUT

Reference Voltage

Reference Output Current3

1.14

1.20

1.26

100

REFERENCE INPUT

Input Compliance Range

Reference Input Resistance

Small Signal Bandwidth

TEMPERATURE COEFFICIENTS

Offset Drift

Gain Drift (Without Internal Reference)

Gain Drift (With Internal Reference)

Reference Voltage Drift

POWER SUPPLY

Supply Voltages

AVDD

DVDD

Analog Supply Current (IAVDD)

Digital Supply Current (IDVDD)4

Digital Supply Current (IDVDD)5

Supply Current Sleep Mode (IAVDD)

Power Dissipation4 (5 V, IOUTFS = 20 mA)

Power Dissipation5 (5 V, IOUTFS = 20 mA)

Power Dissipation6 (5 V, IOUTFS = 20 mA)

Power Supply Rejection Ratio7—AVDD

Power Supply Rejection Ratio7—DVDD

0.1

3

2.7

–0.4

–0.025

1

0.5

0

± 50

± 100

± 50

5

5

71

5

8

380

420

450

1.25

5.5

5.5

75

7

15

12.0

410

450

+0.4

+0.025

OPERATING RANGE

–40

+85

NOTES

1Measured at IOUTA, driving a virtual ground.

2Nominal full-scale current, IOUTFS, is 32 times the IREF current.

3An external buffer amplifier with input bias current <100 nA should be used to drive any external load.

4Measured at fCLOCK = 25 MSPS and fOUT = 1.0 MHz.

5Measured at fCLOCK = 100 MSPS and fOUT = 1 MHz.

6Measured as unbuffered voltage output with IOUTFS = 20 mA and 50 Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz.

7± 10% Power supply variation.

Specifications subject to change without notice.

Units

Bits

LSB

LSB

LSB

LSB

% of FSR

% of FSR

% of FSR

% of FSR

dB

mA

V

kΩ

pF

V

nA

V

MΩ

MHz

ppm of FSR/°C

ppm of FSR/°C

ppm of FSR/°C

ppm/°C

V

V

mA

mA

mA

mA

mW

mW

mW

% of FSR/V

% of FSR/V

°C

–2–

REV. B

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