AD9765-EB 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

AD9765-EB

12-Bit, 125 MSPS Dual TxDAC+® D/A Converter

Analog Devices 

AD9765

IREF1

RSET1

2k⍀

FSADJ1

0.1␮F REFIO

IREF 2

RSET2

2k⍀

FSADJ2

1.2V REF

GAINCTRL

5V

CLK1/IQCLK CLK2/IQRESET

AVDD

PMOS

CURRENT

SOURCE

ARRAY

PMOS

CURRENT

SOURCE

ARRAY

AD9765

SLEEP

CLK

DIVIDER

DAC 1

LATCH

DAC 2

LATCH

ACOM

SEGMENTED

SWITCHES FOR

DAC1

LSB

SWITCH

IOUTA1

IOUTB1

IOUTA2

SEGMENTED

SWITCHES FOR

DAC2

LSB

SWITCH

IOUTB2

MULTIPLEXING LOGIC

MODE

CHANNEL 1 LATCH

CHANNEL 2 LATCH

DVDD

DCOM

WRT1 /

IQWRT

DB0 – DB11

DB0 – DB11

DIGITAL DATA INPUTS

WRT2 /

IQSEL

Figure 20. Simplified Block Diagram

VDIFF = VOUTA – VOUTB

VOUT 1A

VOUT 1B

VOUT 2A

RL1B

50⍀

RL1A

50⍀

VOUT 2B

RL2B

50⍀

RL2A

50⍀

5V

FUNCTIONAL DESCRIPTION

Figure 20 shows a simplified block diagram of the AD9765.

The AD9765 consists of two DACs, each one with its own

independent digital control logic and full-scale output current

control. Each DAC contains a PMOS current source array

capable of providing up to 20 mA of full-scale current (IOUTFS).

The array is divided into 31 equal currents that make up the five

most significant bits (MSBs). The next four bits, or middle bits,

consist of 15 equal current sources whose value is 1/16th of an

MSB current source. The remaining LSB is a binary weighted

fraction of the middle bit current sources. Implementing the

middle and lower bits with current sources, instead of an R-2R

ladder, enhances the dynamic performance for multitone or low

amplitude signals and helps maintain the DAC’s high output

impedance (i.e., >100 kΩ).

All of these current sources are switched to one or the other of

the two output nodes (i.e., IOUTA or IOUTB) via PMOS differen-

tial current switches. The switches are based on a new architec-

ture that drastically improves distortion performance. This new

switch architecture reduces various timing errors and provides

matching complementary drive signals to the inputs of the dif-

ferential current switches.

The analog and digital sections of the AD9765 have separate

power supply inputs (i.e., AVDD and DVDD) that can operate

independently over a 3 V to 5.5 V range. The digital section,

which is capable of operating up to a 125 MSPS clock rate,

consists of edge-triggered latches and segment decoding logic

circuitry. The analog section includes the PMOS current sources,

the associated differential switches, a 1.20 V bandgap voltage

reference and two reference control amplifiers.

The full-scale output current of each DAC is regulated by sepa-

rate reference control amplifiers and can be set from 2 mA to

20 mA via an external resistor, RSET, connected to the Full

Scale Adjust (FSADJ) pin. The external resistor, in combination

with both the reference control amplifier and voltage reference

VREFIO, sets the reference current IREF, which is replicated to the

segmented current sources with the proper scaling factor. The

full-scale current, IOUTFS, is 32 × IREF.

REFERENCE OPERATION

The AD9765 contains an internal 1.20 V bandgap reference.

This can easily be overridden by an external reference with no

effect on performance. REFIO serves as either an input or out-

put, depending on whether the internal or an external reference

is used. To use the internal reference, simply decouple the

REFIO pin to ACOM with a 0.1 µF capacitor. The internal

reference voltage will be present at REFIO. If the voltage at

REFIO is to be used elsewhere in the circuit, an external buffer

amplifier with an input bias current of less than 100 nA should

be used. An example of the use of the internal reference is

shown in Figure 21.

OPTIONAL

EXTERNAL

REFERENCE

BUFFER

ADDITIONAL

EXTERNAL

LOAD

GAINCTRL

AVDD

0.1␮F

+1.2V

REF

REFIO

FSADJ

AD9765

REFERENCE

SECTION

CURRENT

SOURCE

ARRAY

IREF 2k⍀

ACOM

Figure 21. Internal Reference Configuration

An external reference can be applied to REFIO as shown in

Figure 22. The external reference may provide either a fixed

reference voltage to enhance accuracy and drift performance or

a varying reference voltage for gain control. Note that the 0.1 µF

compensation capacitor is not required since the internal refer-

ence is overridden, and the relatively high input impedance of

REFIO minimizes any loading of the external reference.

AVDD

EXTERNAL

REFERENCE

IREF

GAINCTRL

AVDD

+1.2V

REF

REFIO

FSADJ

AD9765

REFERENCE

SECTION

CURRENT

SOURCE

ARRAY

2k⍀

ACOM

Figure 22. External Reference Configuration

REV. B

–9–

Share Link: