AD9768SE 查看數據表（PDF） - Analog Devices
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AD9768SE Datasheet PDF : 4 Pages
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AD9768–SPECIFICATIONS (typical @ +25؇C under following conditions unless otherwise noted; nominal digital
input levels; nominal power supplies; RL = 50 ⍀; RSET = 220 ⍀; VRET = 0 V)
Parameter
Unit
AD9768SJD/SD/SE
RESOLUTION(FS = FULL SCALE)
Bits
8
LSB WEIGHT (CURRENT)
ACCURACY1
Differential Nonlinearity
Integral Nonlinearity
Monotonicity
Zero Offset (lnitial)
µA
± % FS
± % FS
µA
78
0.2
0.2
Guaranteed
60
TEMPERATURE COEFFICIENTS
Zero Offset
Reference Voltage (–1.26 V)
ppm/°C
1.5
ppm/°C
70
DIGITAL DATA INPUTS
Logic Compatibility
Logic Voltage Levels “l” =
“0” =
Coding
ECL
V
–0.9
V
–1.7
Binary (BIN) = Unipolar Out
Offset Binary (OBN) = Bipolar Out
OUTPUT
Current (Unipolar) FS
IOUT (@ Pin 13)
All Digital “1” Input
All Digital “0” Input
IOUT(@ Pin 14)
All Digital “l” Input
All Digital “0” Input
Compliance
Impedance
mA (max)
mA
mA
mA
mA
V (Pin 13)
V (Pin 14)
Ω (± 15%)
2 to 20 (30)
20
0
0
20
–0.7 to +3.0
–1.1 to +3.0
750
SPEED PERFORMANCE
Settling Time (to 0.2% FS)2
Slew Rate
Update Rate
Rise Time
Glitch Energy
ns
5
V/µs
400
MSPS
100
ns
1.8
pV-sec
200
REFERENCE
Internal, Monolithic3
External, Variable4
Voltage-Multiplying Mode
Current-Multiplying Mode
V
V (max)
mA (max)
–1.26
0 to –1.1 (–2)
0 to –5 (–7.5 )
VOLTAGE-MULTIPLYING MODE4 (See Figure 2)
VM Range (at Pin 16)
VM Center
Resistance (at Pin 16)
V
± 0.5
V
–0.6
kΩ
800
Transfer Function –
Measured at Pin 13; Digital “0” Applied
to Bits 1-8:
–0.1 VM Input = 0 mA IOUT
–1.1 VM Input = 0 mA IOUT
Measured at Pin 13; Digital “1” Applied
to Bits 1-8:
Large Signal Bandwidth (–3 dB Point)
–0.1 VM Input = 1 mA IOUT
–1.1 VM Input = 20 mA IOUT
kHz
250
Parameter
CURRENT-MULTIPLYING MODE
(See Figure 4)
IM Range (at Pins 17 & 18)
Resistance (at Pin 18)
Transfer Function –
Large Signal Bandwidth (–3dB Point)
POWER REQUIREMENTS
–5.2 V ± 0.25
+5.0 V ± 0.25
Power Dissipation
Power Supply Sensitivity5
TEMPERATURE RANGES6
Operating
AD9768JD
AD9768SD/SE
Storage
THERMAL RESlSTANCE 7
Junction to Air, θJA (Free Air)
Junction to Case, θJA
PACKAGE OPTION8
Ceramic (D-18)
LCC (E-20A)
Unit
AD9768SJD/SD/SE
mA
0 to 5
Ω
160
Measured at Pin 13; Digital “0” Applied
to Bits 1-8:
1 mA IM Input = 0 mA IOUT
5 mA IM Input = 0 mA IOUT
Measured at Pin 13; Digital “1” Applied
to Bits 1-8:
1 mA IM Input = 4 mA IOUT
5 mA IM Input = 20 mA IOUT
MHz
40
mA (max)
mA (max)
mW (max)
%/%
66(70)
14(15)
410(430)
0.07
°C
0 to +70
°C
–55 to +125
°C
–55 to +150
°C/W
90
°C/W
20
AD9768JD
AD9768SD
AD9768SE
NOTES
1Relative to FS, including linearity (within voltage compliance limits).
2Worst case settling time; includes FS and Most Significant Bit (MSB) transitions.
3Applies when operating AD9768 as standard D/A.
4Based on RL = 50 ohms; RSET = 220 ohms; VRET = 0 V.
51% change in either power supply voltage causes 0.07% change in analog output.
6Case temperature.
7Maximum junction temperature 125°C.
8D = Ceramic DIP, E = Leadless Ceramic Chip Carrier.
Specifications subject to change without notice.
AD9768SD D/A Schematic
–2–
REV. A
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