AD9806 查看數據表（PDF） - Analog Devices
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AD9806 Datasheet PDF : 12 Pages
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AD9806
REGISTER DESCRIPTION
(a) A-REGISTER: Modes of Operation
a1
a0
Modes
0
0
ADC-MODE
0
1
AUX-MODE
1
0
AUXMID-MODE
1
1
CCD-MODE
(Power-On Default
Value = 11)
(b) B-REGISTER: Output Modes
(Default = 00)
b1 b0
00
01
10
11
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Normal
0101010101
1010101010
High Impedance
(c) C-REGISTER: Clock Modes
c1 c0
00
01
10
11
SHP-SHD Clock Pulses
Active Low
Active Low
Active High
Active High
(Default = 00)
Clamp Active Pulses
Active Low
Active High
Active Low
Active High
f) F-REGISTER: AUXMID-Mode PGA (Default = 00 . . . 0)
f 9 f8 f 7 f 6 f5 f 4 f 3 f 2 f 1 f 0 AUXMID–Gain
Gain (512) 1 0 0 0 0 0 0 0 0 0 –4 dB
Gain (1023) 1 1 1 1 1 1 1 1 1 1 +14 dB
Only the 9 LSBs of F-REG are used to adjust gain.
(f) F-REGISTER: AUX-Mode PGA
f9 f8 f7 f6 f5 f4 f3 f2
Gain (128) 1 0 0 0 0 0 0 0
Gain (255) 1 1 1 1 1 1 1 1
(Default = 00 . . . 0)
AUX-Gain
Minimum
Maximum
(g) G-REGISTER: DAC1 Input
(Default = 00 . . . 0)
g7 g6 g5 g4 g3 g2 g1 g0
Code (0) 0 0 0 0 0 0 0 0
Code (255) 1 1 1 1 1 1 1 1
DAC1 Output
Minimum
Maximum
(h) H-REGISTER: DAC2 Input
(Default = 00 . . . 0)
h7 h6 h5 h4 h3 h2 h1 h0 DAC2 Output
Code (0) 0 0 0 0 0 0 0 0
Code (255) 1 1 1 1 1 1 1 1
Minimum
Maximum
(d) D-REGISTER: Power-Down Modes
(Default = 00)
Modes
d1 d0 Description
Normal
0
High Speed 0
Power-Down1 1
Power-Down2 1
0 Normal Operation
1 High-Speed AUX/ADC-MODE
0 Reference Stand-By (Same
Mode as STBY Pin 18)
1 Total Shut-Down
(e) E-REGISTER: Clamp Level Selection (Default = 00)
CLP (0)
CLP (1)
CLP (2)
CLP (3)
e1 e0
00
01
10
11
Clamp Level
32 LSBs
48 LSBs
64 LSBs
16 LSBs
(f) F-REGISTER: CCD-Mode PGA
(Default = 00 . . . 0)
f9 f8 f7 f6 f5 f4 f3 f2 f1 f0
Gain (0) 0 0 0 0 0 0 0 0 0 0
Gain (1023) 1 1 1 1 1 1 1 1 1 1
CCD–Gain
Minimum
Maximum
(j) J-REGISTER: Even-Odd Offset Correction (Default = 0)
j0
Even-Odd Offset Correction
0
Offset Correction In Use
1
Offset Correction Not Used
(m) M-REGISTER: DAC1 and DAC2 PDN
m0
Power-Down of 8-Bit DACs
0
8-Bit DACs Powered Down
1
8-Bit DACs Operational
(Default = 0)
NOTE: With the exception of a write to the PGA register dur-
ing AUX-mode, all data writes must be 10 bits. During an
AUX-mode write to the PGA register, only 8 bits of data are
required. If more than 14 SCK rising edges are applied during a
write operation, additional SCK pulses will be ignored (see
Figure 9). All reads must be 10 bits to receive valid register
contents. All registers default to 0s on power-up, except for the
A-register which defaults to 11. Thus, on power-up, the AD9806
defaults to CCD mode with the 8-bit DACs powered down. Dur-
ing the power-up phase, it is recommended that SL be HIGH
and SCK be LOW to prevent accidental register write operations.
SDATA may be unknown. The RNW bit (“Read/Not Write”)
must be LOW for all write operations to the serial interface, and
HIGH when reading back from the serial interface registers.
–10–
REV. 0
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