AD9806 查看數據表（PDF） - Analog Devices

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AD9806

Complete 10-Bit 18 MSPS CCD Signal Processor

Analog Devices 

TIMING SPECIFICATIONS

AD9806

CCD

N

N+1

N+2

N+3

N+4

SHP

SHD

tINHIBIT

tID

tID

ADCCLK

tOD

tHOLD

ADCCLK RISING EDGE PLACEMENT

D0–D9

N–0

N–9

N–8

N–7

N–6

N–5

NOTES:

1. SHP AND SHD SHOULD BE OPTIMALLY ALIGNED WITH THE CCD SIGNAL. SAMPLES ARE TAKEN AT THE RISING EDGES.

2. ADCCLK RISING EDGE MUST OCCUR AT LEAST 15ns AFTER THE RISING EDGE OF SHP (tINHIBIT).

3. RECOMMENDED PLACEMENT FOR ADCCLK RISING EDGE IS BETWEEN THE RISING EDGE OF SHD AND FALLING EDGE OF SHP.

4. OUTPUT LATENCY IS 9 CYCLES.

5. ACTIVE LOW CLOCK PULSE MODE IS SHOWN.

Figure 1. CCD-MODE Timing

VIDEO

INPUT

ADCCLK

D0–D9

N

N+1

tOD

tHOLD

N–9

N+2

N+3

tID

N–8

N–7

N+4

N–6

NOTE:

EXAMPLE OF OUTPUT DATA LATCHED BY ADCCLK RISING EDGE.

Figure 2. AUX-, AUXMID-, ADC-Mode Timing

N+5

N–5

CCD

SIGNAL

EFFECTIVE

PIXELS

OPTICAL BLACK

BLANKING

INTERVAL

DUMMY BLACK

EFFECTIVE

PIXELS

CLPOB

CLPDM

PBLK

NOTES:

1. CLPOB PULSEWIDTH SHOULD BE A MINIMUM OF 10 OB PIXELS WIDE, 20 OB PIXELS ARE RECOMMENDED.

2. CLPDM PULSEWIDTH SHOULD BE AT LEAST 1␮s WIDE.

3. PBLK IS NOT REQUIRED, BUT RECOMMENDED IF THE CCD SIGNAL AMPLITUDE EXCEEDS 1V p-p.

4. CLPDM OVERWRITES PBLK.

5. ACTIVE LOW CLAMP PULSE MODE IS SHOWN.

Figure 3. CCD-MODE Clamp Timing

REV. 0

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