AD9806 查看數據表（PDF） - Analog Devices

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AD9806

Complete 10-Bit 18 MSPS CCD Signal Processor

Analog Devices 

AD9806

TIMING SPECIFICATIONS (Continued)

VIDEO

SIGNAL

INPUT

CLAMP INTERVAL

(AD9806 INTERNAL

SIGNAL)

H

SYNC

INTERNAL CLAMPING

OCCURS DURING SYNC

NOTE: The AD9806 uses an “automatic” video clamp that senses the most negative in the input signal and uses this level to set the clamp voltage.

As shown in the video waveform above, the SYNC level will be clamped to the black level specified in the E-Register.

Figure 4. AUX-MODE and ADC-MODE Clamp Operation

PGA GAIN CURVE DETAILS

In CCD-Mode, the AD9806 PGA stage provides a gain range

of 0 dB to 34 dB, programmable with 10-bit resolution through

the serial digital interface. The PGA gain curve is divided into

two separate regions. When the PGA Gain Register code is

between 0, and 511, the curve follows a (1 + x)/(1 – x) shape,

which is similar to a “linear-in-dB” characteristic. From Code

CCD-MODE

Code Range Gain Equation (dB)

0–511

512–1023

Gain = 20 log10 ([658 + code]/[658 – code]) – 2.4

Gain = (0.0354)(code) – 2.4

512 to Code 1023, the curve follows a “linear-in-dB” shape. In

AUXMID-Mode, the PGA provides a gain range of –4 dB to

+14 dB, programmable with 9-bit resolution. The exact PGA

gain for either mode can be calculated for any Gain Register

value by using the following equations:

AUXMID-MODE

Code Range Gain Equation (dB)

512–1023 Gain = 20 log10 ([146 + code]/[1170 – code]) – 4

34

28

22

16

10

4

–2

0

127 255 383 511 639 767 895 1023

PGA GAIN REGISTER CODE

Figure 5a. PGA Gain Curve for CCD-Mode

14

11

8

5

2

–1

–4

512

639

767

895

PGA GAIN REGISTER CODE

1023

Figure 5b. PGA Gain Curve for AUXMID-Mode

0.8V

INPUT SIGNAL

??V

0.1␮F

AUXMID

PIN 35

0.4V

5k⍀

–4 dB TO +14dB

PGA

ADC

0.4V

0.4V

9

PGA GAIN

REGISTER

Figure 6. AUXMID-Mode Circuit Block Diagram

–8–

MIDSCALE

REV. 0

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